JPS577973A - Semiconductor nonvolatile memory - Google Patents
Semiconductor nonvolatile memoryInfo
- Publication number
- JPS577973A JPS577973A JP8308180A JP8308180A JPS577973A JP S577973 A JPS577973 A JP S577973A JP 8308180 A JP8308180 A JP 8308180A JP 8308180 A JP8308180 A JP 8308180A JP S577973 A JPS577973 A JP S577973A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- type
- upper layer
- floating gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000010410 layer Substances 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To reduce the write voltage and to enhance integration of a semiconductor nonvolatile memory by a method wherein a region having lower impurity concentration than a substrate is formed at a proper position in the substrate, and the region thereof and a metal floating gate are made to come in contact with each other. CONSTITUTION:P type diffusion layers 2, 2 are formed in the surface layer of the N type silicon substrate 1 being separated at a proper distance and an SiO2 gate oxide film 3 is formed at the upper layer between the diffusion layers 2, 2. The floating gate 4 consisted of Mo is formed at the upper layer thereof, and moreover a gate 7 consisted of Al is formed at the upper layer thereof interposing an SiN4 film 6 between them. The N<-> type region 10 having lower impurity concentration than the substrate 1 is formed in the surface layer of the N type silicon substrate 1 at the proper position in the direction meeting at right angles with the confronting direction of the source and drain, the floating gate 4 is formed extending toward the direction of the formed position of the N<-> type region 10, and is made to come in contact with the N<-> type region 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8308180A JPS577973A (en) | 1980-06-18 | 1980-06-18 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8308180A JPS577973A (en) | 1980-06-18 | 1980-06-18 | Semiconductor nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS577973A true JPS577973A (en) | 1982-01-16 |
Family
ID=13792227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8308180A Pending JPS577973A (en) | 1980-06-18 | 1980-06-18 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS577973A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61232131A (en) * | 1984-10-27 | 1986-10-16 | ル−ドルフ・ハ−フア− | Device for covering single or plurality of filling tube piece for packaging machine with bag with valve to be filledand fitting said bag |
-
1980
- 1980-06-18 JP JP8308180A patent/JPS577973A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61232131A (en) * | 1984-10-27 | 1986-10-16 | ル−ドルフ・ハ−フア− | Device for covering single or plurality of filling tube piece for packaging machine with bag with valve to be filledand fitting said bag |
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