JPS5776642A - Bus monitoring circuit for microprocessor - Google Patents

Bus monitoring circuit for microprocessor

Info

Publication number
JPS5776642A
JPS5776642A JP55153124A JP15312480A JPS5776642A JP S5776642 A JPS5776642 A JP S5776642A JP 55153124 A JP55153124 A JP 55153124A JP 15312480 A JP15312480 A JP 15312480A JP S5776642 A JPS5776642 A JP S5776642A
Authority
JP
Japan
Prior art keywords
signal
space
packaged
counter
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153124A
Other languages
Japanese (ja)
Inventor
Kazuo Onda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55153124A priority Critical patent/JPS5776642A/en
Publication of JPS5776642A publication Critical patent/JPS5776642A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To report a program runaway when a memory space where any I/O is not packaged is accessed, as to the system which outputs a synchronous out (SYNC) signal in the instruction fetch cycle of a microprocessor mu-p. CONSTITUTION:When an I/O group 10 accesses a space where no I/O is packaged, a mu-p1 outputs an SYNC signal 7 to the clock terminal of a counter 20 because of the access of the space other than an I/O-packaged space, bus a CE' signal 19 is outputted from a decoder 18 in the I/O group 10, so that an I/O device 12 does not operate. As a result, when a RESET' signal 29 is high, the output of an NAND gate 27 is low and the counter 20 starts counting. Then, the start of counting holds the output terminal QD of the counter 20 at a high level, and an NMI' signal 8 outputted from an NAND gate 25 is low, so the nonmaskable interruption of the mu- p1 takes place. Consequently, a specific address indicating the kind of a program runaway in the mu-p is sent to an address bus.
JP55153124A 1980-10-31 1980-10-31 Bus monitoring circuit for microprocessor Pending JPS5776642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153124A JPS5776642A (en) 1980-10-31 1980-10-31 Bus monitoring circuit for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153124A JPS5776642A (en) 1980-10-31 1980-10-31 Bus monitoring circuit for microprocessor

Publications (1)

Publication Number Publication Date
JPS5776642A true JPS5776642A (en) 1982-05-13

Family

ID=15555497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153124A Pending JPS5776642A (en) 1980-10-31 1980-10-31 Bus monitoring circuit for microprocessor

Country Status (1)

Country Link
JP (1) JPS5776642A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107454A (en) * 1984-10-30 1986-05-26 Toshiba Corp Bus lock prevention system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107454A (en) * 1984-10-30 1986-05-26 Toshiba Corp Bus lock prevention system

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