JPS577581A - Time generating device - Google Patents

Time generating device

Info

Publication number
JPS577581A
JPS577581A JP8161880A JP8161880A JPS577581A JP S577581 A JPS577581 A JP S577581A JP 8161880 A JP8161880 A JP 8161880A JP 8161880 A JP8161880 A JP 8161880A JP S577581 A JPS577581 A JP S577581A
Authority
JP
Japan
Prior art keywords
circuit
abnormality
signal
time information
display value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8161880A
Other languages
Japanese (ja)
Inventor
Kiyotaka Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8161880A priority Critical patent/JPS577581A/en
Publication of JPS577581A publication Critical patent/JPS577581A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G7/00Synchronisation

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE:To prevent reading of erroneous time information by arranging such that, when there is no change from a valid display value to an invalid display value within a predetermined period, an error is recognized and invalid display value is maintained until a next change takes place. CONSTITUTION:A checking circuit 11 is adapted to continuously check for abnormality of time information delivered by a clock circuit 10 through a timinginformation line 100. When any abnormality is found, the checking circuit 11 informs of the abnormality in the clock circuit 10 by means of a time information error signal transmitted to a gate circuit 30 through a signal line 110. Another checking circuit 21 continuously checks for any abnormality of valid display signal which is delivered thereto by a generating circuit 20 through a signal line 200. When any abnormality is found, the checking circuit 21 delivers a signal through a signal line 210 to the circuit 30 to inform the latter of the abnormality in the circuit 20. The effective display signal to the time receiving device 2 is forcibly maintained as an invalid display value till the next change, when abnormality of time information is detected by the circuit 11 or when abnormality in the effective display signal is detected by the circuit 21.
JP8161880A 1980-06-17 1980-06-17 Time generating device Pending JPS577581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8161880A JPS577581A (en) 1980-06-17 1980-06-17 Time generating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8161880A JPS577581A (en) 1980-06-17 1980-06-17 Time generating device

Publications (1)

Publication Number Publication Date
JPS577581A true JPS577581A (en) 1982-01-14

Family

ID=13751307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8161880A Pending JPS577581A (en) 1980-06-17 1980-06-17 Time generating device

Country Status (1)

Country Link
JP (1) JPS577581A (en)

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