JPS57203107A - Failure discriminator for monitor system - Google Patents

Failure discriminator for monitor system

Info

Publication number
JPS57203107A
JPS57203107A JP8927281A JP8927281A JPS57203107A JP S57203107 A JPS57203107 A JP S57203107A JP 8927281 A JP8927281 A JP 8927281A JP 8927281 A JP8927281 A JP 8927281A JP S57203107 A JPS57203107 A JP S57203107A
Authority
JP
Japan
Prior art keywords
monitor
clock pulse
terminal
failure
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8927281A
Other languages
Japanese (ja)
Other versions
JPH0124397B2 (en
Inventor
Reijiro Aoki
Kenji Hiramine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP8927281A priority Critical patent/JPS57203107A/en
Publication of JPS57203107A publication Critical patent/JPS57203107A/en
Publication of JPH0124397B2 publication Critical patent/JPH0124397B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To increase the reliability of terminal monitor data, by inhibiting the transmission of a clock pulse at a terminal controlling monitor device if a failure takes place in the device and inhibiting the monitor of terminal monitor data at a monitor side when the clock pulse is not received. CONSTITUTION:If a failure takes place in a CPU 1 of a terminal controlling monitor and when a failure signal (e) is transmitted from a watchedog timer 8 to a transmission controller 4 for a prescribed time, since an AND circuit in the device 4 is closed, no clock pulse is given to a monitor display device 6. If a failure takes place in a power supply 7 and a failure signal of power supply (f) is given to the device 4, the clock pulse is not given to the device 6 for a prescribed time. The monitor side does not monitor the terminal monitor data when no clock pulse is received, allowing to receive reliable information only and display it.
JP8927281A 1981-06-09 1981-06-09 Failure discriminator for monitor system Granted JPS57203107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8927281A JPS57203107A (en) 1981-06-09 1981-06-09 Failure discriminator for monitor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8927281A JPS57203107A (en) 1981-06-09 1981-06-09 Failure discriminator for monitor system

Publications (2)

Publication Number Publication Date
JPS57203107A true JPS57203107A (en) 1982-12-13
JPH0124397B2 JPH0124397B2 (en) 1989-05-11

Family

ID=13966101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8927281A Granted JPS57203107A (en) 1981-06-09 1981-06-09 Failure discriminator for monitor system

Country Status (1)

Country Link
JP (1) JPS57203107A (en)

Also Published As

Publication number Publication date
JPH0124397B2 (en) 1989-05-11

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