JPS5755644A - Data terminal equipment - Google Patents
Data terminal equipmentInfo
- Publication number
- JPS5755644A JPS5755644A JP55132005A JP13200580A JPS5755644A JP S5755644 A JPS5755644 A JP S5755644A JP 55132005 A JP55132005 A JP 55132005A JP 13200580 A JP13200580 A JP 13200580A JP S5755644 A JPS5755644 A JP S5755644A
- Authority
- JP
- Japan
- Prior art keywords
- speed
- circuit
- controller
- data
- terminal equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/1438—Negotiation of transmission parameters prior to communication
- H04L5/1446—Negotiation of transmission parameters prior to communication of transmission speed
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To improve the reliability of a data communication system by setting the same transfer speed with a communication controller in the data terminal equipment of the system. CONSTITUTION:A terminal equipment 3 receives through a received data line 2 data transmitted at a transfer speed set in a communication controller 1 and having prescribed bit width, and a pulse extracting circuit 4 extracts and sends a pulse for speed detection to an AND gate 6. Only while the pulse for speed detection is present, a clock from a clock generating circuit 5 is inutted through an AND gate 6 to a counter circuit 7 where it is counted and on the basis of its count value, a speed detecting circuit 8 detects the transfer speed of the controller 1. Then, the circuit 8 controls a speed setting circuit 9 so that a speed coincident with the detected transfer speed is set, and the circuit 9 sends a clock for obtaining the same speed with the controller 1 to a main control circuit 10 to process the data from the controller 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55132005A JPS5755644A (en) | 1980-09-22 | 1980-09-22 | Data terminal equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55132005A JPS5755644A (en) | 1980-09-22 | 1980-09-22 | Data terminal equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5755644A true JPS5755644A (en) | 1982-04-02 |
Family
ID=15071315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55132005A Pending JPS5755644A (en) | 1980-09-22 | 1980-09-22 | Data terminal equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5755644A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61269445A (en) * | 1985-05-24 | 1986-11-28 | Casio Comput Co Ltd | Transmitted data receiving device |
JPS62134741A (en) * | 1985-12-06 | 1987-06-17 | Panafacom Ltd | Serial inputting system |
-
1980
- 1980-09-22 JP JP55132005A patent/JPS5755644A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61269445A (en) * | 1985-05-24 | 1986-11-28 | Casio Comput Co Ltd | Transmitted data receiving device |
JPS62134741A (en) * | 1985-12-06 | 1987-06-17 | Panafacom Ltd | Serial inputting system |
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