JPS5580170A - Duplex computer system - Google Patents

Duplex computer system

Info

Publication number
JPS5580170A
JPS5580170A JP15373578A JP15373578A JPS5580170A JP S5580170 A JPS5580170 A JP S5580170A JP 15373578 A JP15373578 A JP 15373578A JP 15373578 A JP15373578 A JP 15373578A JP S5580170 A JPS5580170 A JP S5580170A
Authority
JP
Japan
Prior art keywords
computer
data
control
succeed
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15373578A
Other languages
Japanese (ja)
Inventor
Isao Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15373578A priority Critical patent/JPS5580170A/en
Publication of JPS5580170A publication Critical patent/JPS5580170A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to succeed smoothly to the control of a process even for anomaly of an operating computer by providing two computers for the control of the process and transmitting always data to the other queuing computer while one computer is operating.
CONSTITUTION: When a switching unit is placed in the position in the figure, process I/O device 2 is connected to computer 11. Computer 11 controls a process on a basis of data inputted from device 2 and stores cumulative data in memory unit 11' and further transmits this data to the other computer 21. Computer 21 stores receiving data in memory unit 21'. During this operation, an anomaly signal is outputted from alarm unit 14 and is inputted to interrupt input device 25 of computer 21 when computer 11 becomes abnormal. Then, device 2 is connected to computer 21 by switching switching unit 1 by computer 21 and can succeed to the process control in stead of computer 11.
COPYRIGHT: (C)1980,JPO&Japio
JP15373578A 1978-12-14 1978-12-14 Duplex computer system Pending JPS5580170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15373578A JPS5580170A (en) 1978-12-14 1978-12-14 Duplex computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15373578A JPS5580170A (en) 1978-12-14 1978-12-14 Duplex computer system

Publications (1)

Publication Number Publication Date
JPS5580170A true JPS5580170A (en) 1980-06-17

Family

ID=15568945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15373578A Pending JPS5580170A (en) 1978-12-14 1978-12-14 Duplex computer system

Country Status (1)

Country Link
JP (1) JPS5580170A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851364A (en) * 1981-09-22 1983-03-26 Hitachi Ltd Doubled peripheral storage controller
US5271013A (en) * 1990-05-09 1993-12-14 Unisys Corporation Fault tolerant computer system
WO1998015899A1 (en) * 1996-10-07 1998-04-16 Hitachi, Ltd. Fault-tolerant computer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851364A (en) * 1981-09-22 1983-03-26 Hitachi Ltd Doubled peripheral storage controller
US5271013A (en) * 1990-05-09 1993-12-14 Unisys Corporation Fault tolerant computer system
WO1998015899A1 (en) * 1996-10-07 1998-04-16 Hitachi, Ltd. Fault-tolerant computer system

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