JPS5470744A - Control output test circuit - Google Patents

Control output test circuit

Info

Publication number
JPS5470744A
JPS5470744A JP13805577A JP13805577A JPS5470744A JP S5470744 A JPS5470744 A JP S5470744A JP 13805577 A JP13805577 A JP 13805577A JP 13805577 A JP13805577 A JP 13805577A JP S5470744 A JPS5470744 A JP S5470744A
Authority
JP
Japan
Prior art keywords
output
data
input
pattern
supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13805577A
Other languages
Japanese (ja)
Inventor
Hideto Nakagawa
Masanori Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13805577A priority Critical patent/JPS5470744A/en
Publication of JPS5470744A publication Critical patent/JPS5470744A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To prevent the wrong control output from being transmitted to the external apparatus and thus to enhance the reliability of the system by forming a circuit to supply again the output of the control system to secure the fault diagnosis at all times for the input/output device within the system.
CONSTITUTION: Input device 1 to supply the data or the signal of the information or the like is installed, along with arithmetic control unit 2 which calculates the data or signal supplied from device 1 to read out the data stored in the internal memory and then writes the data read out as well as delivers th data. Furthermore, output device 3 is provided to convert the output data of unit 2 into the fixed pattern and then trnasmits the pattern to external apparatus 4. In the input/output control system of such constitution, the pattern given from device 3 is sent to apparatus 4, and the transmission line is provided to supply the output patter to deivce 1 again. Then a collation is given via error test part 5 within unit 2 between the pattern supplied again and the data written at the output time, thus deciding the input and output errors for device 1 and 3 respectively.
COPYRIGHT: (C)1979,JPO&Japio
JP13805577A 1977-11-16 1977-11-16 Control output test circuit Pending JPS5470744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13805577A JPS5470744A (en) 1977-11-16 1977-11-16 Control output test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13805577A JPS5470744A (en) 1977-11-16 1977-11-16 Control output test circuit

Publications (1)

Publication Number Publication Date
JPS5470744A true JPS5470744A (en) 1979-06-06

Family

ID=15212919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13805577A Pending JPS5470744A (en) 1977-11-16 1977-11-16 Control output test circuit

Country Status (1)

Country Link
JP (1) JPS5470744A (en)

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