JPS5773941A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5773941A
JPS5773941A JP15018080A JP15018080A JPS5773941A JP S5773941 A JPS5773941 A JP S5773941A JP 15018080 A JP15018080 A JP 15018080A JP 15018080 A JP15018080 A JP 15018080A JP S5773941 A JPS5773941 A JP S5773941A
Authority
JP
Japan
Prior art keywords
film
layer
wiring
integration
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15018080A
Other languages
Japanese (ja)
Inventor
Tomoyasu Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15018080A priority Critical patent/JPS5773941A/en
Publication of JPS5773941A publication Critical patent/JPS5773941A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Abstract

PURPOSE:To make multilayer wiring fine and increase the degree of integration by removing an insulation layer surface and leveling it by arranging an insulation film with a surface layer of Si nitride on an uneven substrate and treating the layer with anisotropic etching after implanting hydrogen ions. CONSTITUTION:Al wiring 3 of the lower layers is formed through openings of an oxide film 2 on a substrate 1 formed with elements. Then a nitride film 4 is accumulated thick by plasma CVD for example. Then ca. 3X10<16>cm<-2> of hydrogen ions 8 are implanted to the above layer with the energy of the range of a half of the thickness of the film which will be removed later. By reactive ion etching process using CF4, the surface of a film 4 is removed. In this etching method, the surface of the film 4 can be leveled, because etching speed at the flat part can be made faster than that at the cavities of ditches. Then wiring at the upper layer is formed highly reliably, and disconnection and short circuit of wires can be avoided because of decrease in unevenness. Also it is possible for multilayer wiring to be more fine, and also the degree of integration can be increased.
JP15018080A 1980-10-28 1980-10-28 Manufacture of semiconductor device Pending JPS5773941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15018080A JPS5773941A (en) 1980-10-28 1980-10-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15018080A JPS5773941A (en) 1980-10-28 1980-10-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5773941A true JPS5773941A (en) 1982-05-08

Family

ID=15491247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15018080A Pending JPS5773941A (en) 1980-10-28 1980-10-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5773941A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181539A (en) * 1983-03-31 1984-10-16 Toshiba Corp Manufacture of semiconductor device
JPS59227124A (en) * 1983-06-08 1984-12-20 Toshiba Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181539A (en) * 1983-03-31 1984-10-16 Toshiba Corp Manufacture of semiconductor device
JPS59227124A (en) * 1983-06-08 1984-12-20 Toshiba Corp Manufacture of semiconductor device

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