JPS59227124A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable highly-precise and highly-efficient etching of a film of Si or an Si compound, by implanting ions selectively into said film on a semiconductor substrate any further by etching this film by a chemical dry etching method. CONSTITUTION:After an SiO2 film 2 is formed on a semiconductor substrate 1, an Si3N4 film 3 is formed on the film 2, and further a metal film 4 is formed on the film 3. Then, a resist pattern 5 having an opening R is formed on the film 4. Next, with the pattern 5 used as a mask, ions of Si, for instance, are implanted into the film 3 through the film 4 exposed inside the opening R, and thereby a region 31 in which ion implantation parts are formed in lines is formed in the opening R. Then, the film 4 is etched by a chemical dry etching (CDE) method with the pattern 5 used as a mask, so as to expose the region 31. When annealing is applied subsequently, a number of stable Si-Si combinations are prepared in Si3N4. When the region 31 is removed by the CDE method with the film 4 used as a mask thereafter, the film 3 is etched selectively, and thus very high precision in etching can be attained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention 1] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can selectively etch etching, etc. with high efficiency and precision. It is related.

[Technical Background of the Invention] In recent semiconductor device production lines, dry etching equipment has come to be used in place of conventional wet etching equipment as processing equipment similar to that of a bevel.

As is well known, the dry etching method uses chemical dry etching that utilizes pure chemical reactions (this includes cylindrical plasma etching, microwave plasma etching, etc., but the following describes the CDE method and In addition to physical etching that uses physical etching action (including sputter etching and ion beam etching), there is also reactive ion etching that uses a combination of chemical reaction and physical action. (abbreviated as RIEFA) is known.

Among these dry etching methods, the CDE method has no risk of damaging the underlying layer, has a high etching speed, and has a high selectivity to the etching target, resulting in a high throughput, and it is also difficult to perform Taber etching. Therefore, it is widely used today.

On the other hand, since the R I method, which has recently been put into practical use as a lithography technique for VLSI, uses anisotropic etching, the side edge m is small, and therefore it is possible to accurately etch patterns with a fine line width of approximately 2 μm without any traces. It has the advantage of being able to

However, since both of the above-mentioned two squares have the following drawbacks, conventional semiconductor device manufacturing methods including these methods also have the following drawbacks.

[Problems with the background technology] Since the ODE method is an etching method that utilizes a chemical reaction, it is essentially isotropic etching. Therefore, the amount of side etching is large, and usually there are variations in the thickness of the film to be etched and etching. Article! Since there is a variation of 1, 3μIl
It is not suitable for pattern processing with a thin line width of 1 or less. For example, with a 2 μm resist pattern, a 0.5 μm
If a thick film to be etched is etched one time using the CD E method, the etching pattern will be 3 μm wide due to isotropic etching, and if a 40% overetch is applied to account for variations in film thickness, the etching pattern will be 3.4 μm wide. The resulting etching pattern is low, and the etching accuracy (ratio of resist pattern to etching pattern) is low, making it impossible to form a high-density, high-precision pattern.

On the other hand, since RIE is an anisotropic etching, it is possible to form patterns with high density and precision, but it damages the underlying layer, so it is used in the J-plane etching process in the manufacturing process of semiconductor devices. In addition, there was a problem in that the throughput was low.

[Object of the Invention] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that has only the advantages of the above two methods but does not have the disadvantages. The purpose is to enable the anisotropic CDE method while taking advantage of the fact that H1 scratches are not generated in the underlying substrate, and thereby to selectively cover thin films etc. with high efficiency and precision. An object of the present invention is to provide a method for manufacturing a device.

Summary of E invention] 3i or Si compound (St 02).

When etching a film of (Si 3N1, etc.) by the CDE method, Si is preliminarily added to the St or Si compound film.

An element such as N, 0.1-1 is ion-implanted (with d3<,
In particular, we focused on the fact that by annealing at a suitable temperature after ion implantation, the etching speed of the ion-implanted region can be made faster or slower than the etching speed of the non-implanted region. , which was used to complete the method of the present invention. That is, the method of the present invention provides a method for adding st to s of a 3i or Si compound (Si 02 , Si 3 N4, etc.) formed on a semiconductor substrate.
,O,N.

By selectively ion-implanting at least 11'fi or more of elements such as 14, etc., and selectively dipping the film using the CR)E method, the film can be formed with a large lead] - without any lumps. It is characterized by being able to perform one tweezing with high precision and high efficiency.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1(a) to FIG. 1(1) are cross-sectional views at each step in the first embodiment of the method of the present invention.

In the same figure, °(, 1 is a Si semiconductor substrate, 2 is S+02
3 is an SI3N4 film, 4 is a metal film made of W (tungsten), etc., and 5 is a resist pattern.

As shown in FIG. 1(a), in the method of the present invention, first, a 5-inch 21112 film (this method is not related to the method of the present invention) is formed on a semiconductor substrate 1, and then a plasma, for example, is applied on the 5i02 film 2. CVD method Csi 3 N41t! A metal film 4 is formed on the Si3N4 IR3 by sputtering, for example.

Finally, the opening R of U1 is etched on the metal film 4 using the normal EP method (etching process). A resist pattern 5 is formed.

Next, as shown in FIG. 1(b), using the resist 1-pattern 5 as a mask, for example, 3i is passed through the metal film 4 exposed in the opening R of the resist pattern 5 to inject Si 3 N The 513Nn film 3 aligns and covers the ion implantation region 31 by inserting the 513Nn film 3 into the opening R of the resist pattern 5.
Formed within.

The ion implantation is performed at the first stage acceleration voltage V. =110keV
, injection mQd=-1,5x10"/c1, second stage y
ac = 2 (iokcV, injection field Q d-3,5
x 10'5/cm'2nd stage Vac=480ke
It is preferable to implant Si over the entire thickness of the st 3 N,l film 3 by overlapping the implantation with V, Qd"5X10"/C11'.

Next, pattern 5 is used as a mask for regimen 1 as shown in Figure 1 (
C) Microphone [-1 wave CDE method [
Gas pressure P (CF4) = 16Pa, P('0
2)=14Pa,? The ion implantation region 31 of the 513N4 film 3 is exposed by opening under the condition of microwave power of 600 W. After that, annealing (800℃) was performed in a nitrogen atmosphere.
, 10 minutes), then the ion-implanted pi/lISi
3N, + medium Ni multim NiQ input L (It'le Ll Substitute a large number of stable 5i-8i atoms in 313Nq
A bonding relationship is created (generally, 3!3N'4 atoms formed by plasma CVD method incorporate many 1-1 atoms, so the implanted Si ions replace H atoms and form 3i- 5i bonds, and annealing promotes this stabilization). Therefore, the ion implantation region 31 becomes a 3i Takafuchimaro region and a large amount of 5i
-8i bond occurs, but as explained later, 5i-3i
Since the bond is relatively easily attacked by CF gas, it is more easily etched by C) gas than other regions.

Next, using the metal film 4 as a mask, the ion-implanted region 31 is removed by the COE method, and as shown in FIG.
The 3N4 film 3 is selectively etched.

In this case, the ion-implanted region 31 has a very high 5illi1 degree, so the etching rate is about 6 times faster than other parts of the 5itNa 193. Although the ion-implanted region 31 is etched rapidly, no Si ion is implanted. The etching time for the etched area is very slow, and the side etching amount is very small (0.1 μl for the conventional method's 1:1 f790.5 μm), making it appear as if W directional etching had been performed. Extremely high accuracy can be obtained. FIG. 2 shows a film MA 31'j which is almost the same as that used in method C in FIG.
The etching characteristics obtained when the conventional ODE method is applied to a semiconductor substrate having 1, which is a "-si 3Na film", and the etching characteristics obtained by the method of the present invention are shown in comparison.

More specifically, the graph shows the relationship between the etching time during overetching and side edge ants in the conventional method and the method of the present invention.

In Fig. 2, the -C1 horizontal axis is the relative one-touching time]-(=
71 - Etching time including bar etching time/Net etching time), and the vertical axis is the hard etching amount ε(
μ111). C(x), the straight line l represents the etching characteristics according to the method of the present invention, and the straight line {circle over (2)} represents the etching characteristics according to the conventional method 1.

Referring to FIG. 2, it can be seen that in the method of the present invention, both the absolute value of the side etch group and the rate of increase in the 4)-side etch ψ are much smaller than in the conventional method.

As described above, it is clear that the amount of side etching can be significantly reduced according to the method of the present invention, and this is due to the following mechanism.

Generally, S:, N is present in the PSi3No film.

H elements are included in the film, and due to these elements, Si-8i, Si-N, 5t-1-1,
Bonds such as N-1-1 are formed. If these bonds are arranged in order of ease of attack by CF4 gas, they are 5I-H,N
-H, >si -si >Si -N, but Si
-1- and N-) (The 1 atom is originally P-8t 3
Although it is not a constituent element of No, it is formed from the composition of the source gas.

After ion implantation of 5i during the formation of a P Sr 3 Ns film containing such a bond, especially when annealing is performed, the 1'' atoms are replaced by 3i atoms in the ion implanted region, forming 5i-8.
The number of i-bonds increases significantly, but in the non-ion-implanted region, due to annealing, the free 1-1 atoms of C are expelled to the outside and the 1-1 atoms in S: -t1 are replaced by N, resulting in Si -N The coupling will continue to increase significantly.

Therefore, while the etching rate increases in the ion-implanted region, the etching speed decreases in the non-ion-implanted region, which is essentially isotropic etching.
Even if E is performed, it is possible to obtain the same turning effect as when performing anisotropic etching.

In the above embodiment, a silicon nitride film was used as the j4x cutting edge, but the method of the present invention can also be applied to a semiconductor JJ board having a silicon oxide film as the film to be etched.

When the method of the present invention is applied to a semiconductor substrate having silicon oxide l1u (P-3iQ, referred to as a film) made by the plasma CV j) method as a film to be etched, p-s;
The main bonds contained in the 02 film are 3i-H, 5i-
0.5i-8i, and when these are arranged in the order of ease of attack by CF and gas, Si -f(>Si -8i >5
It becomes i-0.

After ion-implanting 3i into a predetermined region of P S + 02158, annealing results in 3i- in the ion-implanted region.
3i bonds increase significantly], whereas 5i-0 bonds increase in the non-ion-implanted region, so the ion-implanted region
On the other hand, the non-ion-implanted region is less susceptible to etching by CF4.

When the method of the present invention is applied to a semiconductor substrate having a P-8io film as a film to be etched, one of the ion implantation regions
The cutting speed is c2~3 compared to that in the non-ion implanted region.
It was about double that.

For the above reasons, various types of film processing methods are realized by changing the type of ions implanted into the film to be etched and the annealing temperature.

For example, by implanting N or 0 into the polycrystalline 3i film, the etching speed of the non-etched region is reduced, while the etching speed of the non-ion-implanted etching region is relatively increased. It is also possible to perform different anisotropic CD, E additions.

In the illustrated embodiment, s+ 3N4 n%3 is deposited by using the tungsten l)+ metal film 4 as a mask, but the metal film 4 may be omitted.

FIGS. 3(a) to 3(C) show an example in which the method of the present invention is carried out without forming a gold R film, and in the same figures, the same symbols as in FIG. 1 are used (- The part where it is located is the same part e as in Fig. 1.

FIG. 3(a) shows that 3i is ion-implanted into the I=S+aN* film 3 exposed in the opening R of the resist pattern 5.
A state in which an ion implantation region 31 is formed in the iaN4 film 3 is shown.

FIG. 3(b) shows a state in which St in the ion entry region 31 is stabilized by annealing after removing the resist pattern 5.

FIG. 3(C) shows a state in which the ion implantation region has been removed by performing CD E after the state shown in FIG. 3(1)).

As shown in Figure 3 (C), without the metal film, C
After DE, I? was formed on the SI3N4 film 3. fl D3
2 is a tapered hole, and the D edge of I32 has a rounded shape with rounded corners.

In addition, in the method of the present invention as described above, the conventional CD
It has been found that the side angle σ is 115 compared to the E method, and extremely high accuracy can be obtained.

[Effects of the Invention] As explained above, according to the present invention, 1) it is possible to perform anisotropic etching like the RIE method, and 2) the etching process has the same selectivity and high throughput as the conventional method. ■Erasing can be done without damaging the base.■
High-density and high-precision lamination is possible; (1) conventional CD E equipment can be used; (2) shapes of openings, etc. can be easily controlled.

A semiconductor device manufacturing method having the following features is provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram comparing the etching characteristics of the conventional method and the method of the present invention, and FIG. 3 is a diagram showing the etching characteristics of the method of the present invention. FIG. 1 shows an embodiment of the invention. 1... Semiconductor substrate, 2... S+0. membrane, 33.
...3 + 3 N 4 film, 4...metal film, 5.
...Resist pattern, 31...Ion implantation region,
32...Opening. Figure 1 IJHJ↓↓1111↓Ill Figure 2 1+r Figure 3

Claims (1)

[Claims] 1. After selectively implanting ions of at least one of s+, N, O, and I-1 into a 3i or 3i compound film formed on a semiconductor substrate, the Si or 3i compound film is A method for manufacturing a semiconductor device characterized by chemically dry etching a film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after ion implantation, annealing is performed and then chemical dry etching is performed.