JPH01184832A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01184832A JPH01184832A JP530188A JP530188A JPH01184832A JP H01184832 A JPH01184832 A JP H01184832A JP 530188 A JP530188 A JP 530188A JP 530188 A JP530188 A JP 530188A JP H01184832 A JPH01184832 A JP H01184832A
- Authority
- JP
- Japan
- Prior art keywords
- ion
- semiconductor substrate
- implanted
- etching
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000005530 etching Methods 0.000 abstract description 20
- 238000000137 annealing Methods 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
げ）産業上の利用分野
本発明は半導体装置の製造方法に関し、特に半導体基板
上に形成された絶縁膜の所定部分を除去する方法に関゛
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for removing a predetermined portion of an insulating film formed on a semiconductor substrate.
（ロ）従来の技術
半導体基板上に形成された絶縁膜は、表面安定化のため
の保護膜、イオン注入後のアニール工程に２いて、半導
体基板表面から該半導体基板の構成元素が蒸発するのを
防止する保護膜等として用いられ、重要な役割を果して
いる。(b) Conventional technology The insulating film formed on the semiconductor substrate is a protective film for surface stabilization, and during the annealing process after ion implantation, the constituent elements of the semiconductor substrate evaporate from the surface of the semiconductor substrate. It is used as a protective film to prevent this, and plays an important role.
通常、絶縁膜に開口部を形成し、この開口部を介して半
導体基板表面から電極を引き出す必要がある。Usually, it is necessary to form an opening in the insulating film and draw out the electrode from the surface of the semiconductor substrate through this opening.
一方、絶縁膜に開口部を形成する方法としては、イオン
ビームエツチング（ＩＢＥ）法、リアクティブイオンエ
ツチング（ＲＩＢＥ）法、プラズマエツチング法、ウェ
ットエツチング法等があり、夫々に長所、短所を備えて
いる。On the other hand, methods for forming openings in an insulating film include ion beam etching (IBE), reactive ion etching (RIBE), plasma etching, and wet etching, each of which has its own advantages and disadvantages. There is.
従って、何れの方法を採用するかが非常に大切となる。Therefore, which method to adopt is very important.
体基板表面に物理的イオン衝撃を加え、該基板表”ｇｌ
、；７：＋゛−゛−“、・
面近傍に損傷を受けた層を形成する虞がある。 −゛（
・プラズマエツチング法を採用すると、ガスプラズマ中
でのラジカルとの反応により、エツチングが進むので、
半導体基板表面近傍の損傷を抑えるなだらかなテーパ状
の等方性エラへプロファイルしか得ることができない。By applying physical ion bombardment to the surface of the substrate, the surface of the substrate "gl
,;7:+゛-゛-“,・ There is a risk of forming a damaged layer near the surface. −゛(
・When using the plasma etching method, etching progresses due to the reaction with radicals in the gas plasma.
Only a gently tapered isotropic profile can be obtained that suppresses damage near the surface of the semiconductor substrate.
エツチングが等方的に進むとパターン制御が難しく微細
化に適さない。If etching proceeds isotropically, pattern control is difficult and unsuitable for miniaturization.
同様にウェットエツチング法を採用すると、半い。Similarly, if the wet etching method is used, the result will be half that.
また、半導体基板上に形成された絶縁膜のエツチング速
度は、プロセス中で受ける熱処理（イオン注入後のアニ
ール処理等）により低ドするので、該絶縁膜の加工性が
低ドする。Furthermore, the etching rate of an insulating film formed on a semiconductor substrate is lowered by heat treatment (such as annealing treatment after ion implantation) during the process, resulting in lower workability of the insulating film.
ｅｌ 発明が解決しようとする課題
上述のように従来の技術には、■半導体基板表面近傍に
損傷を与える（ＩＢＥ法、ＲＩＢＥ法）。el Problems to be Solved by the Invention As mentioned above, the conventional techniques include: (1) causing damage near the surface of a semiconductor substrate (IBE method, RIBE method);
■開口部の断面形状が等方性エツチングプロファイルに
なる（プラズマエツチング法、ウェットエツチング広）
。■プロセス中の熱処理により絶縁膜の加工性が低下す
る。という課題がある。■The cross-sectional shape of the opening becomes an isotropic etching profile (plasma etching method, wide wet etching)
. ■The workability of the insulating film decreases due to heat treatment during the process. There is a problem.
に）課題を解決するための手段
本発明は、半導体基板上に形成された絶縁膜の所定部分
にイオン注入を行った後、前記所定部分を除去すること
を特徴とする半導体装置の製造方法である。B) Means for Solving the Problems The present invention provides a method for manufacturing a semiconductor device, which comprises implanting ions into a predetermined portion of an insulating film formed on a semiconductor substrate, and then removing the predetermined portion. be.
（ホ）作用
本発明によれば、半導体基板上の絶縁膜の所定部分にイ
オン注入することにより、前記所定部分の原子同士の結
合力が弱められるので、前記所定部分のエツチング速度
が増大する。(E) Function According to the present invention, by implanting ions into a predetermined portion of an insulating film on a semiconductor substrate, the bonding force between atoms in the predetermined portion is weakened, so that the etching rate of the predetermined portion is increased.
従って、゛同一絶縁膜内でエツチング速度の異なる部分
（所定部分）を形成できるので、該絶縁膜をエツチング
した場合、異方性エツチングプロファイルを得ることが
できろう
（へ）実施例
以上に、本発明の一実施例を図面に基づいて説明する。Therefore, since it is possible to form portions (predetermined portions) with different etching rates within the same insulating film, it is possible to obtain an anisotropic etching profile when etching the insulating film. An embodiment of the invention will be described based on the drawings.
第１図（ａｌ乃至ｆｄｌは本発明の一実施例の工程説明
図である。FIG. 1 (al to fdl are process explanatory diagrams of an embodiment of the present invention.
まず、半絶縁性ＧａＡｓ基板（半導体基板）（１）にイ
オン注入を行い、イオン注入層（２）を形成する（第１
図（ａ））。First, ions are implanted into a semi-insulating GaAs substrate (semiconductor substrate) (1) to form an ion-implanted layer (2) (first
Figure (a)).
続いて、アニールに８いて、半絶縁性ＧａＡｓ基ゝ゛う
で１５分間のアニールを行なう（第１図（ｂｌ ）。な
お、アニールにより、ＳｉＮ膜（３）のエツチング速度
は、アニール前に比べ約１／２−１７８に減少する。Subsequently, during annealing, the semi-insulating GaAs base is annealed for 15 minutes (Fig. 1 (bl)). Due to the annealing, the etching rate of the SiN film (3) is approximately 50% lower than before the annealing. It decreases to 1/2-178.
次に、ＳｉＮ膜（３）に所定のパターンを有したレジス
ト（４）を形成し、このレジスト（４）をマスクトシて
イオン注入を行なう（第１図ＩＣ））。このイオン注入
は半絶縁性ＧａＡｓ基板（１）に損傷を与えないよ分
邪
４゛７
を示す図であり、前記３通りの注入条件の関係を示す。Next, a resist (4) having a predetermined pattern is formed on the SiN film (3), and ions are implanted using this resist (4) as a mask (FIG. 1IC)). This ion implantation is carried out so as not to damage the semi-insulating GaAs substrate (1). This figure shows the relationship among the three implantation conditions.
ＳｉＮ膜（３）に選択的にイオン注入を行った後、該Ｓ
ｉＮ膜（３）を緩衝フッ酸液（フッ化アンモニウム：フ
ッ酸＝ｂ ： １ （体積比、２５℃））を用いて、エ
ツチングし、開口部（５）を形成する（第１図（ｄｌ
）。この場合のエツチング速度と注入量の関係は第３図
に示す如くなり、注入量とともにエツチング速度が増加
する傾向にある。After selectively implanting ions into the SiN film (3), the S
The iN film (3) is etched using a buffered hydrofluoric acid solution (ammonium fluoride: hydrofluoric acid = b: 1 (volume ratio, 25°C)) to form an opening (5) (see Figure 1 (dl)).
). The relationship between the etching rate and the implantation amount in this case is as shown in FIG. 3, and the etching rate tends to increase with the implantation amount.
例えば、注入エネルギー４０ ＫｅＶ 、注入ｍｓ、＜
１０”ｃｌｌの注入条件でイオン注入された領域のエツ
チング速度は、イオン注入されていない領域のそれに比
べ約２倍になることが理解される。従って、開口部（５
）の形状は半絶縁性ＧａＡｓ基板（１）表面に損傷を与
えないウェットエツチングであっても、異方性エツチン
グプロファイルとなり、また、エツチング速度が増大す
るから加工性が向上する。For example, implantation energy 40 KeV, implantation ms, <
It is understood that the etching rate of the ion-implanted region under the 10"cll implantation condition is approximately twice that of the non-ion-implanted region.
) has an anisotropic etching profile even when wet etching does not damage the surface of the semi-insulating GaAs substrate (1), and the etching rate increases, resulting in improved workability.
なお、半導体基板としてはＧａＡｓ以外にＳｉ。Note that the semiconductor substrate may be Si in addition to GaAs.
ＧａＰ等を、絶縁膜としてはＳｉＮ以外に５ｉＯ２Ａｌ
！Ｎ、ｋｅ２０５ 等を、注入イオントシテハＳｉ以外
にＡｓ、Ｓｅ等を用いることができろう（ト） 発明
の効果
本発明方法は以上の説明から明らかな如く、絶縁膜に開
口部を形成する場合、■半導体基板表面近傍に損傷を与
えない。■異方性エツチングプロファイルの開口部を得
ることができるう■エツチング速度が増大するので加工
性が向上する。という効果を得ることができる。GaP, etc., and 5iO2Al other than SiN as the insulating film.
! In addition to Si, As, Se, etc. may be used for implantation of N, Ke205, etc. (g) Effects of the Invention As is clear from the above description, when forming an opening in an insulating film, it is possible to use As, Se, etc. ■Do not cause damage near the surface of the semiconductor substrate. ■ Openings with an anisotropic etching profile can be obtained. ■ Processability is improved because the etching speed is increased. This effect can be obtained.
とキャリア製置の関係を示す図、第３図は注入量とエツ
チング速度の関係を示す図である。
（１）・・・半絶縁性ＧａＡｓ基板（半導体基板）、（
２）・・・イオン注入層％（３）・・・窒化シリコン膜
（絶縁膜）、（４）・・・レジスト、（５）・・・開口
部。FIG. 3 is a diagram showing the relationship between implantation amount and etching rate. (1) Semi-insulating GaAs substrate (semiconductor substrate), (
2)...Ion implantation layer% (3)...Silicon nitride film (insulating film), (4)...Resist, (5)...Opening.
Claims (1)
オン注入を行った後、前記所定部分を除去することを特
徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, which comprises implanting ions into a predetermined portion of an insulating film formed on a semiconductor substrate, and then removing the predetermined portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP530188A JPH01184832A (en) | 1988-01-13 | 1988-01-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP530188A JPH01184832A (en) | 1988-01-13 | 1988-01-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01184832A true JPH01184832A (en) | 1989-07-24 |
Family
ID=11607430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP530188A Pending JPH01184832A (en) | 1988-01-13 | 1988-01-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01184832A (en) |
-
1988
- 1988-01-13 JP JP530188A patent/JPH01184832A/en active Pending
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