JPS60148139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to easily end an etching, which is performed on the protruded parts of an insulating film deposited on the surface of the Si substrate of a semiconductor device, by a method wherein impurities are introduced in the protruded parts only of the insulating film from the surface and only the rate of the etching, which is performed on the protruded parts, is quickened. CONSTITUTION:First, etching-resistant masks 23 are formed in a semiconductor substrate 21, and after that, an etching is selectively performed on the field region and a recessed part is formed. A channel stopper layer 24 of a field is formed by performing an ion-implantation using the masks 23 respectively as a mask. After then, an insulating film 25 is deposited on the whole surface of the substrate 21. Moreover, a fluid substance film 26 is formed on the insulating film 25 in such a way that the surface of the film 26 becomes nearly flat. Impurities are introduced in the protruded parts only of the insulating film 25 using the fluid substance film 26 as a mask. After that, the protruded parts 27 of the insulating film 25 are selectively removed using an etching method, by which an etching rate at a time when impurities are introduced becomes faster than that at a time when impurities are not introduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device, and particularly to improvements in element isolation technology for integrated circuits that are becoming increasingly finer.

[Prior art and its problems]

As semiconductor integrated circuits have become more highly integrated and elements have become smaller, it has become necessary to miniaturize element isolation.

In the conventional selective oxidation method (LOCO8), bird's beaks occur, making it difficult to isolate elements of 2 μm or less.

Instead of LOGO8, an element isolation method (BOX) has been proposed in which the element isolation region of the substrate is etched to form a recess, and an insulating film is buried in the recess so that the surface remains flat. An example of the substrate process will be described with reference to FIG.

First, recesses are selectively formed in the St substrate (1), and then SiOt (21) is deposited on the entire surface by CVD, and the surface is flattened with a T resist film (3) by spin code (Fig. a). ) This post-resist film (3) and 8+02
The entire surface of the film (2) is etched by reactive ion etching (RIE) with the etching rate set to be the same for both until the substrate surface is exposed (Figure b). After this, the desired device is etched using a well-known process. form.

However, in this method, the insulating film (2) is etched from the surface and the etching is terminated when the surface of the convex portion of the 84 substrate is exposed, but this control is difficult. In other words, variations in the thickness of the insulating film (2)! : Due to variations in RIE, over-etching must be performed, and this over-etching causes the height of the insulating film surface to be lower than the surface of the convex portion of the Si substrate. (
(See Figure 0) For this reason, complete flattening is impossible,
The margins in the manufacturing process are also small. Further, there is a drawback that electric field concentration near the surface of the convex portion of the SI substrate causes deterioration of transistor characteristics such as an increase in leakage current with log Id-Vg characteristics.

[Purpose of the invention]

The purpose of the present invention is to increase the etching rate by introducing impurities into only the convex portions of the insulating film from the surface, and thereby slow down the etching rate when the convex portions of the υSt substrate surface are exposed. , the etching of the insulating film on the surface of the convex portion of the Si substrate can be performed with good control.

[Summary of the invention]

In the present invention, first, an etching-resistant mask is formed on a conductor substrate, and then the field region is selectively etched to form a recess, and then a channel stopper layer for the field is formed by ion implantation using the etching-resistant mask as a mask. Then, an insulating film is deposited in the recesses over the entire surface of the substrate. A fluid material film is then formed on this insulating film so that the surface is substantially flat. Then, using this fluid material film as a mask, impurities are introduced only into the convex portions of the insulating film. after that.

Using the fluid material film as a mask, only the convex portions of the insulating film are etched using an etching method in which the etching rate is faster when impurities are introduced than when no impurities are introduced. In this manner, desired elements are formed in the element forming regions separated by the flatly buried insulating film.

〔Effect of the invention〕

According to the present invention, it becomes easy to control the etching when etching the insulating film, and the etching of the insulating film can be easily completed on the surface of the convex portion of the Si substrate. That is, by forming in the same insulating film portions with impurities introduced and portions without impurities in a well-controlled manner, it is possible to widen the etching margin for burying all four parts of the insulating film by simply changing the etching rate.

In addition, variations such as variations in etching and variations in insulating films can be absorbed by over-etching by providing a difference in etching of the insulating film, and can be absorbed within this over-etching time. This eliminates variations in Tr properties, prevents variations in Tr properties, and provides high yield and high reliability.

Further, the etching conditions for the fluid material film and the insulating film can be varied over a wide range, that is, the margin is widened.

For example, the fluid material film and the insulating film may be etched separately or simultaneously.

Further, since reactive ion etching (RIE), which is expensive and causes the formation of a damaged layer, is not necessarily required for etching the insulating film, there is an advantage that it can be formed by a low-cost process.

In this way, it is possible to easily achieve complete planarization with little variation and to embed the insulating film with good reproducibility.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

First, prepare a p-1 substrate 21 with a plane orientation (100) of 5 to 10Ω-1, and then apply an etching-resistant mask and an ion implantation mask on the substrate. For example, use a thermal oxide film C'6 method to selectively etch a to form.

After that, using the 8iN film (c) as a mask, the Si substrate (2υ is et'g about 0.6 μm using KOH, for example. After that, for example, the Si substrate surface L21) is covered with a thermal oxide film (300
After forming a field channel stopper layer Q (not shown) using SiN as a mask, a field channel stopper layer Q (a) is formed by the ion implantation method in step 1. The order of thermal oxidation and channel stopper formation may be reversed.

Ge07! 1llilrKf Fumien pasting 1" x 8" 0. A film (c) of about 0.7 μm is formed. Furthermore, for example,
By forming a photoresist (c), the surface of the Si substrate is made flat. Then use Photoregis as a mask.
By ion implantation, 1 is injected into the Si0g part of the field part through the resist layer into the CVD-8i of the convex part of the Si substrate.
n, ions are implanted only into the film to form a 5-ins film Qη containing B. (Figure 2 (a)) Back side! For example, by etching only the upper part of the photoresist using 02 plasma, the surface of the 8 i 0x film (5) containing pB is exposed. (FIG. 2b) Thereafter, the 5iOz film gradient containing B is selectively removed by etching with NH4F, for example. At this time, the SiO□ film (c) containing B was damaged by 2 to 5
Etched more than twice as fast. For example, t is 1xlO"l
Even with a small amount of a&, twice the etching speed was obtained. Thereafter, the remaining photoresist (a) is removed using 02 plasma.

(FIG. 2C) After that, the SiN film C23) is coated with, for example, CF,
Thermal oxidation film (24 is NH4F) is removed by CDE (chemical dry etching) containing
Remove by etching. (Fig. 2d) At this time, the edges of the %S + Oz film (c) can be rounded.

Also, although the shape shown in Figure 4 is raised, it does not have to be raised. This swell can be changed by the thickness of the SiN film (c). This allows over-etching of only the film portion.

After this, elements are formed through normal steps.

In this example, N of the part with B (c) and the part without B (c)
For example, if the etching rate for H and F' is 3
If there is a difference of 04 times between 200 A/min and 800 A/min, it will take about 2 minutes and 12 seconds to etch (5). In addition to this, as the SiN film (c) part, (
C) can be oat-etched for 2 minutes and 30 seconds. This means that it is possible to oat-etch more than about 100%, and the margin for embedding in the four parts of 5 in 2 is greatly widened, making it easier. In addition, in the normal process, the overetching is 20% (the variation in the formed film is usually within 10%), so the field insulating film seems to have a raised edge on the convex part of the Si substrate, as shown in Figure 2 (d). Tr
There is no deterioration in characteristics. Since it is formed with a further bulge, the margin is widened by the bulge against film burrs in the field in a later process. Furthermore, since NH and F are used, there are advantages in that the process can be performed at low cost, the processing is simple, and the throughput can be increased. Also HIE
Since etching such as etching is not used, there is no formation of a damage layer, and a highly reliable element is formed without any consideration for reliability.

Furthermore, since B has a light mass, ions can be implanted deeply even if the accelerating voltage is relatively low. For example, it is sufficient to implant B++ ions double-charged to 300, so there is no need for such a high acceleration voltage, and the field oxide film thickness is becoming thinner, so in the future it may be possible to use low acceleration. Therefore, it becomes even more advantageous. Also,
Since the SiN film acts as a stopper against the penetration of B into the convex portion of the Si substrate, there is no effect on the Si substrate.

Also, 8iN g 0!3 Oyo U Si 0zll!
(Although it remains after the 23t CVD-S i 02 test, it may be removed before the CVD-8iOx deposit.

Further, although the B ion implantation distribution is shown in the entire convex portion in FIG. 2(a), it may be shown only in the upper part of the 8iN film.

This method can simplify the ion implantation process.

Further, the taper angle of the side wall of the recess may be in the range of 90° to 45°. A combination of these may also be used.

In addition, ions such as B may be implanted at the location shown in Figure 2 (bl).Furthermore, even if ions such as B penetrate the St substrate surface, it does not matter if the amount is small compared to the amount of channel ion implantation. .Also, if it passes through, it can be made electrically neutral by ion-implanting impurities of the opposite conductivity type.Also,
This step may also serve as a channel dose.

[Other embodiments of the invention]

The type of impurity may be other than B. For example, P.

It may be As, etc. (Inert elements such as Ar or Xe may also be used.

Any other element can be j5s by ion implantation.
The faster the etching of jO, the better.

Further, although etching was performed using NH and F, other etching methods may be used. For example, dry etching such as RIE using CF4 or HF-based etching may be used.

In this case, the photoresist and the insulating film may be etched at the same time. In such a case, etching conditions should be selected such that etching is stopped at the first mask material.

Also, although Sin and SiN were used as the first mask,
It may be made of a single layer or may be made of other materials such as pot y S'
+At, 03. A combination of these or a single layer may be used.

The thickness of the insulating film should be equal to or greater than the difference between the recesses.A single layer of photoresist was used as the fluid material film.
A multilayer structure of two or more layers may be used. In addition to the resist film,
It is also possible to use a glass film such as spin-on glass, polyimide, or PSG that melts through low-temperature heat treatment.

Further, the insulating film may be densified by heat treatment.

Also, as explained in NMO8, PMO8, bipolar, 0
It can be applied to MO8, 808, etc.

Although ion implantation was used to introduce impurities, a thermal diffusion method may also be used. Alternatively, ion beam lithography may be used; in this case, there is no need for flattening and no mask.

[Brief explanation of drawings]

FIGS. 1(a) to 1(C) are cross-sectional views showing a conventional element isolation process, and FIGS. 2(al to d) are cross-sectional views showing an embodiment of the present invention. In the figures, 1. 21...84 substrate, 22...5iOz, 23...
...SiN film, 24...Channel stopper F, 2,
25...SrOx film, 3.26...Resist film, 27...SiO□ film containing B. Agent: Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2

Claims (1)

[Claims] a step of forming a first layer of at least one mask material on a semiconductor substrate and forming a recess in a field region using the first mask material as a mask; a step of forming a first insulating film on the entire surface of the substrate; forming a second film of at least one layer so as to flatten the surface of the substrate; and introducing an impurity into at least a portion of the convex portion of the first insulating film.
The first insulating film is formed in the recess by forming a third film whose etching rate is faster than in the part of the insulating film where impurities are not introduced, and by selectively etching and removing the third film. A method for manufacturing a semiconductor device, comprising the step of leaving behind.