JPS5967632A - Preserving method for alignment mark of wafer - Google Patents
Preserving method for alignment mark of waferInfo
- Publication number
- JPS5967632A JPS5967632A JP57177589A JP17758982A JPS5967632A JP S5967632 A JPS5967632 A JP S5967632A JP 57177589 A JP57177589 A JP 57177589A JP 17758982 A JP17758982 A JP 17758982A JP S5967632 A JPS5967632 A JP S5967632A
- Authority
- JP
- Japan
- Prior art keywords
- alignment mark
- alignment
- wafer
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000004321 preservation Methods 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 241001092070 Eriobotrya Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体集積回路の製造工程において、ウェ
ハーのアライメントマークを保存する方法に関し、竹に
、第ｎ回目のウェハー］−程で膜質Ｎでアライメントマ
ークを作った場合に第（ｎ＋１）回以雁でこのアライメ
ントマークの領域を膜４４へ・Ｉでカバーをほどこして
おくことで、それ以降のプロセスで）Ｉ！ｌｔＮをエツ
チングする工作を通してもアライメントマークが損傷さ
れないようにして、アライメントマークのコントラスト
の向上、アライメント１１１度の向上、チップ上のアラ
イメントマーり領域の減少を期するようにしたものであ
る。[Detailed Description of the Invention] The present invention relates to a method for preserving alignment marks on a wafer in the manufacturing process of semiconductor integrated circuits. From the (n+1)th time onward, the region of this alignment mark is covered with film 44 and I, so that in the subsequent process) I! The alignment mark is not damaged even through the LTN etching process, and the purpose is to improve the contrast of the alignment mark, improve the alignment of 111 degrees, and reduce the alignment mark area on the chip.
従来のウェハーアライメントマークの保存方法は第１図
（ａ）、第１図（ｂ）に示すように行われており、この
うち、第１図（ａ）はアライメントマーク部の断面を示
すものである。この第１図（ａ）に示すように、たとえ
ばＳｉ基板１に第１回目の工程において、ＬＯＣＱ号（
Ｌｏｃａｌ ０ｘｉｄａｔｉｏｎ ｏｆ３ｉ１ｉｃｏｎ
）構造の５ｉｎ２膜によって７ライメントマ一ク部２
を形成する。The conventional method for storing wafer alignment marks is shown in Figures 1(a) and 1(b), of which Figure 1(a) shows a cross section of the alignment mark. be. As shown in FIG. 1(a), for example, in the first process, LOCQ (
Local Oxidation of3i1icon
) Structure of 5in2 film allows 7 alignment mask part 2
form.
このアライメントマーク部２はいくつかの酸化工程、エ
ツチング工程を経ることによって、第１図（ａ）に示し
た尚さｈｌが５ｉｎ２膜がエツチングされることにより
除々に減少していくが、特にコンタクト工程では図に示
した膜３がＰＳＧなどの５ｉｎ２糸の膜の場合、エツチ
ング工程が終了すると第１図（ｂ）に示したように、高
さ１１１から高さｈ２に大幅に減少し、的さｂ ２ ｔ
ｔｌかなり小さなものとなる。This alignment mark portion 2 undergoes several oxidation steps and etching steps, and the hl shown in FIG. 1(a) gradually decreases as the 5in2 film is etched. In the process, when the membrane 3 shown in the figure is a 5in2 membrane such as PSG, when the etching process is completed, the height decreases significantly from 111 to height h2 as shown in Figure 1(b), and the target is sa b 2 t
tl becomes quite small.
このアライメントマーク部２にＡ／などの不透明な膜４
を＃崩すると、Ａ／ホトリン工程でのアライメントマー
ク部２のコントラストが大幅に減少し、アライメント精
度が低下するという欠点がめった。An opaque film 4 such as A/ is placed on this alignment mark portion 2.
When # is broken, the contrast of the alignment mark portion 2 in the A/photorin process is greatly reduced, and alignment accuracy is often reduced.
この発明は上記従来の欠点を除去するためになされたも
ので、アライメントマークのコントラストの向上、アレ
イメン） ２０度の向上、チップのアライメントマーク
領域の減少を期することのできるウェハーアライメント
マークの保存方法を提供することを目的とする。This invention was made to eliminate the above-mentioned conventional drawbacks, and includes a method for storing wafer alignment marks that can improve the contrast of alignment marks, improve the alignment mark angle by 20 degrees, and reduce the area of alignment marks on chips. The purpose is to provide
以下、この発明のウェハーアライメントマーりの保存方
法の笑施例について図面に基づき説明する。第２図（ａ
）および第２図（ｂ）はそれぞれその一実施例の工８説
明図である。まず、第２図（ａ）に示すようにたとえは
半導体基板としてＳｉ基板１１を用いて、ＬＯＣＯり］
二程でアライメントマークをイ乍る場合Ｓｉ基也１１に
ｒ、ｏｃｏｓ工程で５ｉ０２のアライメントマーク１２
ン形成し、次のｐｏｌｙ” Ｓｉ （ポリ−シリコン）
工程に秒いてアライメントマーモ
バー１３でアライメントマーク１２の鎖酸をカバーシて
おく。これによシ、後の工程の酸化膜エツチング工程で
ＰＳＧなとの酸化膜１４のエツチング工程においても、
ｐｏｌｙ −Ｓｔと耐化ＩＥＪ１４の間でエツチングの
魚択比か太さいために、カバー１３はエツチングされず
アライメントマーり１２の段差ｈ３はそのま壕保存され
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the wafer alignment mark preservation method of the present invention will be described with reference to the drawings. Figure 2 (a
) and FIG. 2(b) are explanatory diagrams of step 8 of one embodiment thereof, respectively. First, as shown in FIG. 2(a), for example, using a Si substrate 11 as a semiconductor substrate, LOCO
When adding alignment marks in the second step, add r to Si base 11, and add alignment mark 12 to 5i02 in ocos process.
The next poly”Si (poly-silicon)
After a few seconds in the process, cover the chain acid of the alignment mark 12 with an alignment marmobar 13. Due to this, even in the oxide film 14 etching process of PSG in the oxide film etching process in the later process,
Since the etching selection ratio between the poly-St and the hardened IEJ 14 is large, the cover 13 is not etched and the step h3 of the alignment mark 12 is preserved as it is.
このため、後の工程で第２図（ｂ）のようにＡＩなどの
不透明な膜１５をウニノ・−上に蒸着した場合にも段Ｍ
ｈａ 中ｈ４であり、アライメントマーク１２のコン
トラストが従来に比較して向上する。Therefore, even if an opaque film 15 such as AI is deposited on the surface of the layer M as shown in FIG. 2(b) in a later process,
ha is medium h4, and the contrast of the alignment mark 12 is improved compared to the conventional one.
これによυアライメント精度の向上、スループットの改
善、また別工相でアライメントマークを作り直すことが
無くなるためアライメントマーク１２の数を減らせると
いうＡＩ」点が有る。This has the advantage of improving υ alignment precision, improving throughput, and reducing the number of alignment marks 12 because it eliminates the need to recreate alignment marks in a separate engineering phase.
なお、膜質に関しては、ＬＯＧＯ８工程と酸化膜エツチ
ングの関係の他に、１４１コンタクト工程で作ったマー
クに最初のＡＩでカバーを作り、第２回目以降のコンタ
クト工程に対して、１＞ １コンタクト工程で作ったマ
ークがエツチングされることなく１Ａ：存するようにし
てもよい。Regarding the film quality, in addition to the relationship between the LOGO8 process and oxide film etching, the mark made in the 141 contact process is covered with the first AI, and for the second and subsequent contact processes, 1>1 contact process. 1A: may be made so that the mark made in 1A remains without being etched.
また、第１回目のＡＩなどの不央明な膜の蒸着工程で作
ったマークに対して仄の層聞杷Ｕ農工程でカバー４作り
、以後のＡＩなどの不坊明なＪ換の形成工程に対して、
第１回目のＡｌなどの不坊明なノ良の形成工程で作った
マーク上の絶縁酸化ＩＮカッ９−によりエツチングされ
ることなくマークの保存が可能であるなど多々組合せが
ある。In addition, cover 4 was created in the thin layer loquat U process for the marks created in the first AI and other vague film deposition processes, and subsequent AI and other vague J replacements were formed. For the process,
There are many combinations, such as the insulating oxidized IN cup 9- on the mark made in the first process of forming an unrefined material such as Al, making it possible to preserve the mark without being etched.
以上のように、この発明のウェハーアライメントマーク
の保存方法によれば、第１のマークでアライメントマー
クを形成し、第２の膜でこのアライメントマーク上にカ
バーを形成し、この力・々−によりアライメントマーク
をエツチングから保藤するようにしだので、アライメン
トマークのコントラストが匠米に比較して向上し、アラ
イメント精度の向上、スループットの改善、アライメン
トマークの数を減少できる効果を奏する。As described above, according to the method for preserving a wafer alignment mark of the present invention, an alignment mark is formed using the first mark, a cover is formed over the alignment mark using the second film, and this force is applied to the alignment mark. Since the alignment mark is changed from etching to etching, the contrast of the alignment mark is improved compared to the takumai method, which has the effect of improving alignment accuracy, improving throughput, and reducing the number of alignment marks.
第１図（ａＪおよび第１図（ｂ）はそれぞれ従来のウェ
ハーアライメントマークの保存方法全説明するだめの工
程説明図、第２図（ａ）および第２図（ｂ） ｔ「よそ
れぞれこの発明のウニノー−アライメントマークの保存
方法の一実施例を説明するための工程説明図である。
１１・・・Ｓｉ基板、１２・・・アライメントマーク、
１３・・・カバー、１４・・・酸化膜、Ｊ５・・・不透
明な刀体。
特許出願人 沖電気工業株式会社
（ａ）
第２
（ａ）
１図
（ｂ）
図
（ｂ）
１４１−Figure 1 (aJ and Figure 1 (b) are process explanatory diagrams that do not fully explain the conventional method for preserving wafer alignment marks, Figure 2 (a) and Figure 2 (b) respectively. It is a process explanatory diagram for explaining an example of a method for preserving an alignment mark of 11...Si substrate, 12... alignment mark,
13... Cover, 14... Oxide film, J5... Opaque sword body. Patent applicant Oki Electric Industry Co., Ltd. (a) Section 2 (a) Figure 1 (b) Figure (b) 141-
Claims (1)
、第２の膜でこのアライメントマーク上にカバーを形成
し、このカバーにより上記アライメントマークをエツチ
ングから保護することを特徴とするウェハーアライメン
トマークの保存方法。A wafer alignment mark characterized in that an alignment mark is formed on a semiconductor substrate with a first film, a cover is formed on the alignment mark with a second film, and the cover protects the alignment mark from etching. Preservation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57177589A JPS5967632A (en) | 1982-10-12 | 1982-10-12 | Preserving method for alignment mark of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57177589A JPS5967632A (en) | 1982-10-12 | 1982-10-12 | Preserving method for alignment mark of wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5967632A true JPS5967632A (en) | 1984-04-17 |
Family
ID=16033627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57177589A Pending JPS5967632A (en) | 1982-10-12 | 1982-10-12 | Preserving method for alignment mark of wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5967632A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03142820A (en) * | 1989-10-27 | 1991-06-18 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JP2008218656A (en) * | 2007-03-02 | 2008-09-18 | Denso Corp | Manufacturing method of semiconductor device, and semiconductor wafer |
| CN105845555A (en) * | 2015-01-14 | 2016-08-10 | 南京瀚宇彩欣科技有限责任公司 | Semiconductor device and manufacturing method therefor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5180777A (en) * | 1975-01-13 | 1976-07-14 | Hitachi Ltd | |
| JPS5447583A (en) * | 1977-09-22 | 1979-04-14 | Hitachi Ltd | Silicon gate type mis semiconductor device |
| JPS5662324A (en) * | 1979-10-26 | 1981-05-28 | Seiko Epson Corp | Semiconductor device position fitting method |
| JPS5664432A (en) * | 1979-10-29 | 1981-06-01 | Seiko Epson Corp | Positioning of semiconductor device |
-
1982
- 1982-10-12 JP JP57177589A patent/JPS5967632A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5180777A (en) * | 1975-01-13 | 1976-07-14 | Hitachi Ltd | |
| JPS5447583A (en) * | 1977-09-22 | 1979-04-14 | Hitachi Ltd | Silicon gate type mis semiconductor device |
| JPS5662324A (en) * | 1979-10-26 | 1981-05-28 | Seiko Epson Corp | Semiconductor device position fitting method |
| JPS5664432A (en) * | 1979-10-29 | 1981-06-01 | Seiko Epson Corp | Positioning of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03142820A (en) * | 1989-10-27 | 1991-06-18 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| JP2008218656A (en) * | 2007-03-02 | 2008-09-18 | Denso Corp | Manufacturing method of semiconductor device, and semiconductor wafer |
| CN105845555A (en) * | 2015-01-14 | 2016-08-10 | 南京瀚宇彩欣科技有限责任公司 | Semiconductor device and manufacturing method therefor |
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