JP2001210578A - Method for manufacturing stencil masking - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance production efficiency by developing a process for improving etching accuracy and shortening manufacturing process, in the manufacturing of a stencil masking which aims at reducing the influence of microloading effect in a dry etching production process in the manufacturing process, and to enhance the dimensional accuracy of in a masking face. SOLUTION: A stencil mask manufacturing process in the preceding back etching process includes forming gradations of a film thickness of a resist left in a pattern field, after developing by adjusting the amount of exposed light, and selectively thinning a masking substrate film in a minute pattern formation field, with an aspect ratio higher than that of the surrounding region, prior to patterning.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stencil-type mask for electron beam lithography used for manufacturing a semiconductor or the like.

[0002]

2. Description of the Related Art Conventionally, in electron beam lithography used for fine patterning in semiconductor manufacturing, a Si substrate or a pattern transfer mask is used as a pattern transfer mask to improve throughput.
A stencil mask that processes an SOI substrate and opens a pattern region is used. However, in the stencil mask described above, in the dry etching process in the manufacturing process, the dimensional accuracy in the mask plane is impaired due to the effect of the microloading effect in a high aspect ratio region having a fine pattern dimension and a low aspect ratio region in which it is not so. The phenomenon occurs. As a method for solving this, there is known a method of reducing the thickness of a mask substrate in a region having a fine pattern dimension and a high aspect ratio. However, the conventional manufacturing method still has a problem in terms of shortening the process.

[0003]

SUMMARY OF THE INVENTION The present invention relates to the manufacture of a stencil mask having the above-mentioned structure.
It is an object of the present invention to provide a method for improving yield and improving productivity by shortening a process.

[0004]

According to a first aspect of the present invention, there is provided a method of manufacturing a stencil mask in which a substrate thickness in a high aspect ratio forming region is reduced, the method comprising the steps of:
Forming a first resist film on the second Si substrate of the SOI substrate on which the substrate and the second Si substrate are formed; and
Removing and patterning the first resist film in the high aspect ratio forming region of the SOI substrate, and engraving the second Si substrate by etching using the pattern of the first resist film as a mask, Removing the first resist film, forming a new second resist film on the second Si substrate, and forming the second resist film in the high aspect ratio forming region and the low aspect ratio forming region of the SOI substrate. Removing the second resist film and patterning, using the pattern of the second resist film as a mask,
The low aspect ratio forming region of the SOI substrate is dug the second Si substrate up to the insulating film, and the high aspect ratio forming region is the second aspect to a desired depth that can reduce the difference between the low aspect ratio forming region and the aspect ratio. Digging the Si substrate, the insulating film and the first Si substrate, removing the second resist film, and forming a third resist film on the first Si substrate Patterning the third resist film, digging the first Si substrate using the pattern of the third resist film as a mask, removing the third resist film, the insulating film And a step of removing

According to a second aspect of the present invention, there is provided a method of manufacturing a stencil mask in which the thickness of a substrate in a high aspect ratio formation region is reduced, the method comprising the steps of:
A step of forming a first resist film on the second Si substrate of the SOI substrate on which the substrate is formed, and increasing the height of the SOI substrate by making a difference in exposure amount with respect to the first resist film. Performing a patterning process of giving a gradation to the remaining resist thickness of the aspect ratio forming region and the low aspect ratio forming region, and using the pattern of the first resist film as a mask, the low aspect ratio forming region extends to the insulating film by the second process. The second Si substrate, the insulating film and the first Si substrate are dug down to a desired depth where the high aspect ratio forming region can reduce the difference between the aspect ratio and the low aspect ratio forming region. Digging step, a step of removing the first resist film, a step of forming a second resist film on the first Si substrate, and patterning the second resist film,
Using the pattern of the second resist film as a mask, the first resist
A step of digging a Si substrate; a step of removing the second resist film; and a step of removing the insulating film.

According to the method of manufacturing a stencil mask according to the first aspect of the present invention, in the process of manufacturing a stencil mask for reducing the influence of the microloading effect and improving the dimensional accuracy of the mask, a stencil mask is formed in a preceding back etching step. By selectively patterning the resist film in the high-aspect-ratio forming area to reduce the thickness of the mask substrate in the high-aspect-ratio forming area, the amount of engraving by etching the mask substrate in the high-aspect-ratio forming area is accurately controlled. It becomes possible.

Further, according to the stencil mask manufacturing method according to the second aspect of the present invention, the resist film in the high aspect ratio forming region is selectively formed in the preceding back etching step in order to reduce the thickness of the mask substrate in the high aspect ratio forming region. When patterning into a pattern, the exposure is adjusted to give gradation to the remaining resist film thickness, and the thinning of the high aspect ratio forming area and the back etching of all the pattern areas are simultaneously performed in a single etching process. It is possible to shorten the process and increase the production efficiency.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. Embodiments 1 and 2 FIG. 1 is a cross-sectional view illustrating a method for manufacturing a stencil mask according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view illustrating a method for manufacturing a stencil mask according to Embodiment 2 of the present invention. It is. 1 and 2, 1 is a Si substrate (upper layer),
2 SiO ₂ or the like of the insulating film, the Si substrate (lower layer) 3, 4a, 4b,
4c is a resist film (lower layer), 5 is a fine pattern high aspect ratio forming area (fine pattern forming area), 6 is a low aspect ratio forming area with a large pattern dimension, and 7 is a resist film (upper layer).

Next, with regard to the method of manufacturing a stencil mask of the present invention, first, matters common to the first and second embodiments will be described in detail. As an example, the reduction ratio of the electron optical system is 4 times, the thickness of the Si substrate (upper layer) 1 is 2 μm, and the thickness of the insulating film 2 is 1
In the case of transferring a fine pattern of 0.10 μm width and a pattern of 0.25 μm width with the same mask under the condition of μm and the thickness of the Si substrate (lower layer) 3 of 725 μm, the opening width on the stencil mask is 0.40 μm. 1.0 μm, and the aspect ratios are 1: 5 and 1: 2, respectively. Conditions for dry etching
With the conventional method, 0.40μm
The high-aspect-ratio forming region (fine pattern forming region) having an m width is about 0.18 μm on average, and is thicker than the design dimensions.

On the other hand, in the method of manufacturing a stencil mask according to the first and second embodiments of the present invention, a high aspect ratio forming region (fine pattern forming region) 5 having a width of 0.40 μm is formed before a pattern opening step by dry etching. Si
The substrate (upper layer) 1 is removed by 1.2 μm in the depth direction by etching. By reducing the thickness of the high aspect ratio forming region (fine pattern forming region) 5, the aspect ratio of the high aspect ratio forming region (fine pattern forming region) 5 becomes 1: 2, and the aspect ratio in the mask surface becomes constant. As a result, even if the dry etching conditions are adjusted to an opening with a width of 1.0 μm,
The dimensional error of the high aspect ratio forming region (fine pattern forming region) 5 having a width of 0.40 μm can be suppressed to ± 0.02 μm or less.

Next, a method of manufacturing a stencil mask according to the first embodiment will be described in detail with reference to FIG.
First, as shown in FIG. 1A, a Si substrate (upper layer) 1 (first Si substrate), an insulating film 2 and a Si substrate (lower layer) 3 (second Si
A resist film 4a (first resist film) is formed on a Si substrate (lower layer) 3 on an SOI substrate composed of a (substrate). Next, as shown in FIG. 1B, the resist film 4 is patterned to form a concave pattern as the high aspect ratio forming region 5. Next, as shown in FIG. 1C, after the Si substrate 3 is dug by etching using the pattern of the resist film 4a as a mask, the resist film 4a is removed. Next, as shown in FIG. 1D, a new resist film 4b (second resist film) is formed on the Si substrate (upper layer) 1 by coating. Next, as shown in FIG. 1E, the resist film 4b is patterned. Next, as shown in FIG. 1 (f), the Si substrate 1 ( The upper layer is dug, and the low aspect ratio formation region 6 is
(Lower layer) is dug, and then the resist film 4 is removed. Next, as shown in FIG. 1 (g), the Si substrate 1 (upper layer)
A resist film 7 (third resist film) is formed on the substrate 1 by coating. Next, as shown in FIG. 1H, the resist film 7 is patterned. Next, as shown in FIG. 1I, the Si substrate 1 is dug using the pattern of the resist film 7 as a mask, and then the resist film 7 is removed. After that, the insulating film 2 is removed. By the above method, a stencil mask in which the substrate thickness in the high aspect ratio formation region (fine pattern formation region) is reduced can be manufactured.

In the stencil mask manufacturing method according to the first embodiment described above, only the Si substrate (lower layer) 3 in the high aspect ratio forming region (fine pattern forming region) 5 is etched to a desired depth (FIG. 1 ( c)) Then, a resist film is applied again (FIG. 1D), and after the resist film in all the pattern regions is patterned, etching is performed (FIG. 1E). In this manufacturing process, there is a time difference in signal detection of the insulating film 2 between the high aspect ratio forming region (fine pattern forming region) 5 and the other region, and the time difference is used for etching conditions to dig for thinning. The filling amount can be controlled with high accuracy. When the etching selectivity between the Si substrate and the insulating film is 1: 5, the Si substrate (lower layer) 3 in the high aspect ratio forming region (fine pattern forming region) 5 is dug by 6 μm etching. At this time, the anisotropy of the etching does not matter much. Then, the Si substrate (upper layer) 1 in the high aspect ratio forming region (fine pattern forming region) 5 is 1.2 μm ± 0.2 μm due to a time difference when the insulating film is etched.
A thin film could be formed with the accuracy of.

As described above, according to the stencil mask manufacturing process of the first embodiment, in the process of manufacturing a stencil mask for reducing the influence of the microloading effect and improving the dimensional accuracy of the mask, a high aspect ratio is obtained in the preceding back etching step. By selectively patterning the resist film in the high aspect ratio formation area to reduce the thickness of the mask substrate in the formation area, it is possible to accurately control the amount of engraving by etching the mask substrate in the high aspect ratio formation area. become.

Next, a method of manufacturing a stencil mask according to the second embodiment will be described in detail with reference to FIG.
First, as shown in FIG. 2A, a Si substrate (upper layer) 1 (first Si substrate), an insulating film 2 and a Si substrate (lower layer) 3 (second Si
A resist film 4c (first resist film) is formed on a Si substrate (lower layer) 3 on an SOI substrate composed of a (substrate). Next, as shown in FIG. 2 (b), the high aspect ratio forming region 5 and the low aspect ratio forming region 6
Is performed to give a gradation to the remaining resist film thickness.
Next, as shown in FIG. 2C, using the pattern of the resist film 4c as a mask, the high-aspect-ratio forming region 5 and the low-aspect-ratio forming region 6 reach a desired depth where the difference in aspect ratio can be reduced. In the low aspect ratio formation region 6, the Si substrate 3 is dug up to the insulating film 2, and thereafter, the resist film 4c is removed. Next, as shown in FIG. 2D, a resist film 7 (second resist film) is formed on the Si substrate (upper layer) 1 by coating. Next, as shown in FIG. 2E, the resist film 7 is patterned. Next, FIG.
As shown in (f), the Si substrate 1 is dug using the pattern of the resist film 7 as a mask, and then the resist film 7 is removed. After that, the insulating film 2 is removed. By the above method, a stencil mask in which the substrate thickness in the high aspect ratio forming region (fine pattern forming region) is reduced can be manufactured.

In the stencil mask manufacturing method according to the second embodiment described above, when the resist film 4c in the high aspect ratio forming region (fine pattern forming region) 5 is selectively patterned, the amount of exposure is adjusted by adjusting the exposure amount. By giving a gradation to the film thickness (FIG. 2B), the thinning of the high aspect ratio forming region (fine pattern forming region) 5 and the back etching of all the pattern regions are simultaneously performed in one etching step (FIG. 2B). 2 (c)) From the stencil mask manufacturing method described in the first embodiment, the Si substrate in the high aspect ratio forming region (fine pattern forming region) 5
(Step (c)) of etching only (lower layer) 3 and step of applying, exposing and developing a resist film (FIG. 1 (d))
, And the process can be greatly shortened.

As described above, according to the stencil mask manufacturing process of the second embodiment, the resist film in the high aspect ratio forming region is selectively patterned to reduce the thickness of the mask substrate in the high aspect ratio forming region in the preceding back etching step. In this case, by adjusting the exposure amount to give gradation to the remaining resist film thickness, the thinning of the high aspect ratio forming region and the back etching of all the pattern regions are simultaneously performed in a single etching process, thereby reducing the manufacturing process. Shortening can be realized and production efficiency can be further increased.

[0017]

As described above in detail, by using the present invention, a stencil mask capable of processing a dimension within a mask surface with high precision even in a case where various pattern dimensions are mixed can be manufactured in a short process. Can be produced. As a result, the mass production yield and productivity of the stencil mask in which the high aspect ratio formation region (fine pattern formation region) is thinned can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a stencil mask according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of a stencil mask according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate (upper layer) 2 Insulating film 3 Si substrate (lower layer) 4a, 4b, 4c Resist film (lower layer) 5 High aspect ratio formation area (fine pattern formation area) 6 Low aspect ratio formation area 7 Resist film (upper layer)

Claims (2)

[Claims] A first Si substrate and a second Si substrate sandwiching an insulating film;
Forming a first resist film on the second Si substrate of the SOI substrate on which the substrate is formed, and removing and patterning the first resist film in a high aspect ratio forming region of the SOI substrate And a step of using the pattern of the first resist film as a mask
Engraving a Si substrate by etching; removing the first resist film; forming a new second resist film on the second Si substrate; and a high aspect ratio of the SOI substrate. Removing and patterning the second resist film in the formation region and the low aspect ratio formation region, and using the pattern of the second resist film as a mask, the SOI
The low aspect ratio forming region of the substrate is dug the second Si substrate up to the insulating film, and the high aspect ratio forming region is the second Si substrate to a desired depth capable of reducing the difference between the low aspect ratio forming region and the aspect ratio. Digging a substrate, the insulating film, and the first Si substrate; removing the second resist film; and forming a third resist film on the first Si substrate. Patterning the third resist film, digging the first Si substrate using the pattern of the third resist film as a mask, removing the third resist film, and removing the insulating film. And removing the stencil mask with a reduced thickness of the substrate in the high aspect ratio formation region. 2. A first Si substrate and a second Si substrate with an insulating film interposed therebetween.
Forming a first resist film on the second Si substrate of the SOI substrate on which the substrate is formed, and increasing the height of the SOI substrate by making a difference in an exposure amount with respect to the first resist film. Performing a patterning process for giving a gradation to the remaining resist thickness of the aspect ratio forming region and the low aspect ratio forming region; and, using the pattern of the first resist film as a mask, the low aspect ratio forming region extends to the insulating film. The second Si substrate, the insulating film and the first Si substrate are dug down to a desired depth where the high aspect ratio forming region can reduce the difference between the aspect ratio and the low aspect ratio forming region. Digging; removing the first resist film; forming a second resist film on the first Si substrate; patterning the second resist film; Resist film A step of digging the first Si substrate using a pattern as a mask; a step of removing the second resist film; and a step of removing the insulating film. A method for manufacturing a stencil mask having a reduced thickness.