JPS5766591A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS5766591A JPS5766591A JP55143229A JP14322980A JPS5766591A JP S5766591 A JPS5766591 A JP S5766591A JP 55143229 A JP55143229 A JP 55143229A JP 14322980 A JP14322980 A JP 14322980A JP S5766591 A JPS5766591 A JP S5766591A
- Authority
- JP
- Japan
- Prior art keywords
- difference
- time constant
- memory cells
- bit lines
- blr
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To fetch stored information accurately at a high speed by lessening the unbalance of a readout potential, by connecting dummy cells to bit lines between memory cells. CONSTITUTION:Dummy word lines DWLL and DWLR are positioned near the centers of bit lines BLL and BLR respectively, and dummy cells CDR and CDR are connected to the bit lines BLL and BLR nearly in the center between memory cells. Consequently, when a difference in time constant is worst, the closest and farthest memory cells to and from a sense amplifier are selected in the figure (B); the difference in time constant at this time is the product RBXCBX(1/2) of the halved resistance RB of a bit line and capacity CB and it is reduced to half that in the figure (A) to improve the difference greatly, thereby reducing the unbalance of a readout potential due to the difference in time constant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55143229A JPS5766591A (en) | 1980-10-13 | 1980-10-13 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55143229A JPS5766591A (en) | 1980-10-13 | 1980-10-13 | Memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5766591A true JPS5766591A (en) | 1982-04-22 |
Family
ID=15333896
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55143229A Pending JPS5766591A (en) | 1980-10-13 | 1980-10-13 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5766591A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000051869A (en) * | 1999-01-27 | 2000-08-16 | 김영환 | Open bit-line dram cell array |
-
1980
- 1980-10-13 JP JP55143229A patent/JPS5766591A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000051869A (en) * | 1999-01-27 | 2000-08-16 | 김영환 | Open bit-line dram cell array |
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