JPS5758295A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5758295A
JPS5758295A JP56119062A JP11906281A JPS5758295A JP S5758295 A JPS5758295 A JP S5758295A JP 56119062 A JP56119062 A JP 56119062A JP 11906281 A JP11906281 A JP 11906281A JP S5758295 A JPS5758295 A JP S5758295A
Authority
JP
Japan
Prior art keywords
cell
read out
memory
appeared
differentially
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56119062A
Other languages
Japanese (ja)
Other versions
JPS603706B2 (en
Inventor
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56119062A priority Critical patent/JPS603706B2/en
Publication of JPS5758295A publication Critical patent/JPS5758295A/en
Publication of JPS603706B2 publication Critical patent/JPS603706B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize a memory LSI in high speed and highly stable operation, by locating digit lines differentially in close location. CONSTITUTION:Data lines D0, -D0 on which differential readout signals are appeared, are located in parallel closingly, and a memory cell MC is connected to only one cross point among cross points between one word line W and DW. When a memory is read out, the D0, -D0 are precharged to the same voltage, and the said W is selected to read out the cell, and the DW is selected and a dummy cell DM connected to the -D0 which is not connected to the cell is read out at the same time, and a differential voltage appeared on the D0, -D0 is differentially amplified at a preamplifier PA.
JP56119062A 1981-07-31 1981-07-31 semiconductor memory Expired JPS603706B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119062A JPS603706B2 (en) 1981-07-31 1981-07-31 semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119062A JPS603706B2 (en) 1981-07-31 1981-07-31 semiconductor memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14805674A Division JPS5539073B2 (en) 1974-12-25 1974-12-25

Publications (2)

Publication Number Publication Date
JPS5758295A true JPS5758295A (en) 1982-04-07
JPS603706B2 JPS603706B2 (en) 1985-01-30

Family

ID=14751954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119062A Expired JPS603706B2 (en) 1981-07-31 1981-07-31 semiconductor memory

Country Status (1)

Country Link
JP (1) JPS603706B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3538053A1 (en) * 1984-10-26 1986-05-07 Mitsubishi Denki K.K., Tokio/Tokyo SEMICONDUCTOR STORAGE DEVICE

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3538053A1 (en) * 1984-10-26 1986-05-07 Mitsubishi Denki K.K., Tokio/Tokyo SEMICONDUCTOR STORAGE DEVICE

Also Published As

Publication number Publication date
JPS603706B2 (en) 1985-01-30

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