JPS5766589A - Semiconductor storage element - Google Patents

Semiconductor storage element

Info

Publication number
JPS5766589A
JPS5766589A JP55143131A JP14313180A JPS5766589A JP S5766589 A JPS5766589 A JP S5766589A JP 55143131 A JP55143131 A JP 55143131A JP 14313180 A JP14313180 A JP 14313180A JP S5766589 A JPS5766589 A JP S5766589A
Authority
JP
Japan
Prior art keywords
input
voltage
polarity
chip selection
storage element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55143131A
Other languages
Japanese (ja)
Inventor
Toshiyuki Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55143131A priority Critical patent/JPS5766589A/en
Publication of JPS5766589A publication Critical patent/JPS5766589A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To increase the degree of freedom of the designing of a device circuit by enabling the polarity of a chip selection input to be inverted. CONSTITUTION:To use a chip selection input CS as a ''1'', a write signal is inputted from a write-in input (a) and through a writing circuit 3, a fuse 2 is blown at a voltage higher than the Zener voltage of a Zener diode 3. In this case, a voltage from a Vcc becomes higher than the earth potential to obtain a positive voltage, which is applied to an EOR gate. Therefore, when the input CS in the ''1'', a -CS is a ''0''. Consequently, an output ''0'' is sent from the EOR gate 1 as the -CS without reference to whether the input CS is the ''0'' or ''1'', and a user inverts the polarity of the input CS freely.
JP55143131A 1980-10-14 1980-10-14 Semiconductor storage element Pending JPS5766589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55143131A JPS5766589A (en) 1980-10-14 1980-10-14 Semiconductor storage element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143131A JPS5766589A (en) 1980-10-14 1980-10-14 Semiconductor storage element

Publications (1)

Publication Number Publication Date
JPS5766589A true JPS5766589A (en) 1982-04-22

Family

ID=15331630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143131A Pending JPS5766589A (en) 1980-10-14 1980-10-14 Semiconductor storage element

Country Status (1)

Country Link
JP (1) JPS5766589A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241085A (en) * 1988-03-22 1989-09-26 Nec Corp Buffer circuit for inputting clock signal
JPH077225U (en) * 1985-06-06 1995-01-31 アルテラ・コーポレーション Programmable macrocell for integrated circuits
US5929653A (en) * 1996-07-30 1999-07-27 Nec Corporation Semiconductor integrated circuit having programmable enabling circuit
FR2786621A1 (en) * 1998-12-01 2000-06-02 France Etat ELECTRIC AND / OR ELECTRONIC SYSTEM INTEGRATED WITH MEANS FOR INSULATING A FUNCTIONAL MODULE, CORRESPONDING ISOLATION DEVICE AND METHOD AND USE

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077225U (en) * 1985-06-06 1995-01-31 アルテラ・コーポレーション Programmable macrocell for integrated circuits
JPH01241085A (en) * 1988-03-22 1989-09-26 Nec Corp Buffer circuit for inputting clock signal
US5929653A (en) * 1996-07-30 1999-07-27 Nec Corporation Semiconductor integrated circuit having programmable enabling circuit
FR2786621A1 (en) * 1998-12-01 2000-06-02 France Etat ELECTRIC AND / OR ELECTRONIC SYSTEM INTEGRATED WITH MEANS FOR INSULATING A FUNCTIONAL MODULE, CORRESPONDING ISOLATION DEVICE AND METHOD AND USE
WO2000033314A1 (en) * 1998-12-01 2000-06-08 ETAT FRANCAIS représenté par LE DELEGUE GENERAL POUR L'ARMEMENT Integrated electric and/or electronic system with means for insulating a functional module, corresponding device and method for insulation and use
US6437959B1 (en) 1998-12-01 2002-08-20 Delegation Generale Pour L'armement Electrical and/or electronic system integrated with an isolating device and method that isolates a functional module

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