KR910001981A - Integrated circuit including programmable circuit - Google Patents

Integrated circuit including programmable circuit Download PDF

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Publication number
KR910001981A
KR910001981A KR1019900001607A KR900001607A KR910001981A KR 910001981 A KR910001981 A KR 910001981A KR 1019900001607 A KR1019900001607 A KR 1019900001607A KR 900001607 A KR900001607 A KR 900001607A KR 910001981 A KR910001981 A KR 910001981A
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KR
South Korea
Prior art keywords
program data
memory device
circuit
volatile memory
nonvolatile memory
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KR1019900001607A
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Korean (ko)
Inventor
마코토 사카모토
Original Assignee
원본미기재
가와사끼 세이데쯔 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 원본미기재, 가와사끼 세이데쯔 가부시끼가이샤 filed Critical 원본미기재
Publication of KR910001981A publication Critical patent/KR910001981A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Debugging And Monitoring (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

프로그램 가능한 회로를 포함하는 집적 회로Integrated circuit including programmable circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 관한 집적회로의 제1실시예를 구성을 나타내는 블록도.1 is a block diagram showing the construction of a first embodiment of an integrated circuit according to the present invention;

제2도는, 본 발명의 제2실시예의 구성을 나타내는 블록도이다.2 is a block diagram showing the configuration of the second embodiment of the present invention.

Claims (4)

⒜ 프로그램 가능한 회로⑴에 관한 프로그램 데이타를 저장하기 위하여 칩상의 프로그램 가능한 회로⑴내에 배치되는 휘발성 메모리소자 ⑵와; ⒝ 상기 칩상에 상기 프로그램 가능한 회로⑴의 외부에 배치되며, 외부로 부터 그의 내부에 프로그램 데이타 기록되도록 하는 불휘발성 메모리소자⑶ 및; ⒞ 상기 불휘발성 메모리 소자⑶내에 기록된 프로그램 데이타 또는 외부단자⑸로 부터 공급되는 프로그램 데이타를 스위칭을 통하여 상기 휘발성 메모리 소자⑵에 전송하는 수단⑷으로 구성되는 집적회로.A volatile memory element disposed in the programmable circuitry on a chip for storing program data relating to the programmable circuitry; (B) a nonvolatile memory element disposed on the chip outside of the programmable circuitry and configured to write program data therefrom from outside; And means for transferring program data recorded in the nonvolatile memory device or program data supplied from an external terminal to the volatile memory device through switching. 제1항에 있어서, 상기 프로그램 데이타를 전송하는 수단은, 클록전원(41)과; 상기 클록전원(41)에 의하여 발생되는 클록을 분할하기 위한 분주회로(42)와; 상기와 같이 분할된 클록을 계수하고 상기 클록과 동기하여 어드레스를 발생하는 카운터(43)와; 상기 불휘발성 메모리 소자⑶의 위드선을 선택하기 위하여 판독어드레스로서의 상기 어드레스를 디코우드 하는 디코우더(44)와; 상기 휘발성 메모리 소자(2)의 위드선을 선택하기 위하여 기록 어드레스로서 상기 카운터(43)에서 발생되는 상기 어드레스를 디코우드하는 디코우더(45)와; 상기 클록과 동기하여 상기 불휘발성 메모리 소자(3)내에 저장된 데이타를 판독하기 위한 검지회로(46)와; 상기 휘발성 메모리소자(2)의 비트선을 구동하기 위하여 외부로 부터 입력되는 제어신호(X)의 지령에 근거하여 외부에 있는 외부단자(5)를 통하여 입력된 프로그램 데이타 또는 상기 건지회로(46)에 의하여 판독된 프로그램 데이타 중의 하나를 선택하는 입력 스위치/기록회로(47)로 구성되는 집적회로.2. The apparatus of claim 1, wherein the means for transmitting the program data comprises: a clock power supply (41); A divider circuit 42 for dividing a clock generated by the clock power supply 41; A counter (43) for counting the divided clocks as described above and generating an address in synchronization with the clocks; A decoder (44) for decoding the address as a read address to select a weed line of the nonvolatile memory device; A decoder (45) for decoding the address generated at the counter (43) as a write address to select the weed line of the volatile memory element (2); A detection circuit (46) for reading data stored in the nonvolatile memory device (3) in synchronization with the clock; The program data or the guernsey circuit 46 input through an external external terminal 5 based on a command of a control signal X input from the outside to drive the bit line of the volatile memory device 2. And an input switch / writing circuit (47) for selecting one of the program data read by. 제1항에 있어서, 상기 프로그램 데이타를 전송하는 수단(4)은, 상기 휘발성 메모리소자(2)내에 저장된 프로그램 데이타를 상기 불휘발성 메모리소자(3)로 전송하기 위한 회로를 포함하는 집적회로.The integrated circuit according to claim 1, wherein said means for transferring program data comprises circuitry for transferring program data stored in said volatile memory element (2) to said nonvolatile memory element (3). 제3항에 있어서, 상기 휘발성 메모리 소자(2)내에 저장된 프로그램 데이타를 상기 불휘발성 메모리 소자(3)로 전송하기 위한 회로는, 검지회로(46)와, 입력 스위치/기록회로(51) 및 전압배율기(52)로 구성되는 집적회로.The circuit for transmitting the program data stored in the volatile memory device 2 to the nonvolatile memory device 3 includes: a detection circuit 46, an input switch / write circuit 51 and a voltage. Integrated circuit composed of a multiplier (52). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900001607A 1988-06-23 1990-02-09 Integrated circuit including programmable circuit KR910001981A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15572188 1988-06-23
JP1159293A JPH0271335A (en) 1988-06-23 1989-06-21 Integrated circuit
JP1-159293 1989-06-21

Publications (1)

Publication Number Publication Date
KR910001981A true KR910001981A (en) 1991-01-31

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Application Number Title Priority Date Filing Date
KR1019900001607A KR910001981A (en) 1988-06-23 1990-02-09 Integrated circuit including programmable circuit

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JP (1) JPH0271335A (en)
KR (1) KR910001981A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5042790A (en) * 1990-02-16 1991-08-27 Xerox Corporation Toggled switch for use in a sheet feed apparatus
JPH09319645A (en) 1996-05-24 1997-12-12 Nec Corp Non-volatile semiconductor memory device

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JPH0271335A (en) 1990-03-09

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