JP2621598B2 - Magnetic disk drive - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a magnetic disk drive used as a data storage device in an information processing device.

[Conventional technology]

A magnetic disk device used as a data recording device in an information processing device is conventionally used as an auxiliary external storage device, so its operation time is not necessarily long, and its life is short (for example, two to three years). There were few cases where troubles occurred due to frequent occurrences of failures, so few equipped with a measuring device for integrating the operating time,
Those equipped with a measuring device also integrate the input power-on time.

[Problems to be solved by the invention]

In recent years, magnetic disk devices have been used for online databases, and moreover, information processing devices themselves have been frequently used without interruption for 24 hours. A mechanism that moves the head to a specified position on the magnetic disk in a sealed container.) The magnetic disk rotation mechanism is deteriorated, and the magnetic disk or magnetic head is dirty. In order to do so, it is necessary to know exactly when the head disk assembly (HDA) was actually used.

The problem to be solved by the present invention, in other words, the object of the present invention is to respond to the above-mentioned requirement for the magnetic disk drive, and to easily know the time when the HDA was actually used, and at a low cost. An object of the present invention is to provide a magnetic disk drive provided with a highly reliable operation integrated time measuring circuit.

[Means for solving the problem]

A magnetic disk drive according to the present invention includes a power-on control circuit that generates a power-on signal when power is turned on, a clock generation circuit that generates first and second clock signals, and a reset circuit that is reset by the power-on signal. The first and second clock signals are input, and the memory read data is sequentially incremented from 0 by the second clock signal until the read data changes from 1 to 0, and thereafter is incremented by a count-up signal at regular time intervals. A memory address signal generating circuit for outputting a counter value as a memory address signal; a memory reset signal reset by the power-on signal; counting the first clock signal by a counter; A memory content update instruction circuit for outputting a signal; The content stored at the address specified by the address signal is output as memory read data, and when the memory write instruction signal is input, the content of the address specified by the memory address signal is set to 1 and provided in the head disk assembly. A memory circuit that writes 1 to the rewritable read-only memory in the direction of a higher address every predetermined time, and an operation integration time display circuit that inputs the memory address signal and displays the content as an operation integration time. A counter which is incremented by inputting the power-on signal to a reset terminal via an inverter and an OR gate and resetting the first clock signal to a clock terminal, and The output signal of the counter is decoded and its value becomes a predetermined value. A decoder which sets its output signal to 1 at the point of time, a first D-type flip-flop which is set by the second clock signal and whose output signal becomes 1 and a set 1 clock after the second clock signal A second D-type flip-flop whose output signal is 1 and an AND of each of the output signals of the first and second D-type flip-flops and the first clock signal, respectively First and second AND gates that output the memory write instruction signal and the count-up signal, and the output signal of the first D-type flip-flop becomes 1 through the OR gate when the output signal becomes 1. The counter is reset.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, when a power is turned on, a power-on control circuit 2 generates a power-on signal 9 used for resetting each circuit when the power is turned on. The clock generation circuit 1
It generates two-phase clock signals 7 and 8. The memory address signal generating circuit 4 receives the power-on signal 9 from the power-on control circuit 2 and the clock signals 7 and 8 from the clock generating circuit 1 and is reset by the power-on signal 9 to read the memory read from the memory circuit 6. Until the data 13 changes from “1” to “0”, 0
, And outputs the value of the counter sequentially incremented as the memory address signal 12. The memory content update instruction circuit 3 is reset by the power-on signal 9, is clocked, counts the signal 7 by a counter, and outputs a memory write instruction signal 11 and a count-up signal 10 every elapse of a predetermined time (for example, every one hour). . The memory circuit 6 outputs the contents stored at the address specified by the memory address signal 12 input from the memory address signal generation circuit 4 as memory read data 13, and outputs the memory write instruction signal 11 Is input, the content of the address specified by the memory address signal 12 is set to 1. The operation integrated time display circuit 5 inputs the memory address signal 12 and displays the content as an operation integrated time by a display means such as a light emitting diode.

FIG. 2 is a circuit diagram showing details of the memory content update instruction circuit of the embodiment of FIG. 1, and FIG. 4 shows the operation of the memory content update instruction circuit of FIG. 2 and the memory address signal generation circuit of FIG. It is a timing chart.

2 and 4, since the power-on signal 9 is input to the reset terminal of the counter 21 via the inverter 27 and the A / O gate 28, the value of the counter 21 is 0 when the power is turned on. The clock signal 7 is input to the clock terminal of the counter 21, and the counter 21 is incremented every time the clock signal 7 is input. Output signal of counter 21
31 is decoded by decoder 22 and its value is 3600
At that time, the output signal 32 becomes 1, the D-type flip-flop 23 is set by the clock signal 8, and the output signal 33 becomes 1. Further, the clock signal 8
One clock later, the D-type flip-flop 24 is set, and its output signal 34 becomes 1. Output signals 33 and 34 are ANDed with clock signal 7 in AND gates 25 and 26, respectively, and output as memory write instruction signal 11 and count-up signal 10, respectively. When the output signal 33 becomes 1, the OR gate 28
The counter 21 is reset via.

FIG. 3 is a circuit diagram showing details of the memory address signal generation circuit of the embodiment of FIG. 1, and FIG. 4 is a timing chart showing the operation of the memory content update instruction circuit of FIG.

3 and 4, the power-on signal 9 is supplied to a D-type flip-flop 45 and an inverter 49 via an inverter 49.
Input to reset terminals 46 and 48 for initial resetting of each D-type flip-flop. The power supply voltage V is applied to the D terminal of the
Therefore, when the power-on signal 9 becomes 1 and the clock signal 7 output first is inputted, the D-type flip-flop 45 is set and the output signal 55 becomes 1. Since the output signal 55 is input to the D terminal of the D-type flip-flop 46, the output signal 56 of the D-type flip-flop 46 becomes 1 when the next clock signal 8 is input. At this time, the reset is released because the negative output signal of the D-type flip-flop 46 is input to the reset terminal of the counter 44. On the other hand, while the gate of the AND gate 42 is open and the D-type flip-flop 41 is 1, the AND gate 42 is synchronized with the timing of the clock signal 8.
A pulse is applied to the clock terminal of the counter 44 via the OR gate 43 and the counter 44 is incremented.

FIG. 4 shows a case where the memory read data 13 becomes 0 when the memory address signal 12 becomes “3”, and at that time, the D terminal of the D-type flip-flop 41 is connected to the memory read data 13. However, since the clock signal 7 is input to the clock terminal, the D-type flip-flop 41 is reset at the time when the clock signal 7 rises, and the increment operation of the counter 44 is interrupted. Thereafter, when the count-up signal 10 is input from the memory content update instruction circuit 3, the counter is output via the OR gate 43.
A pulse is applied to the clock terminal 44, and the counter 44 is incremented.

〔The invention's effect〕

As described above, the magnetic disk drive of the present invention
By providing a rewritable read-only memory in the head disk assembly and adding data every time a fixed time elapses, it is possible to easily know the actual operating time of the HDA, not just the power-on time. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of a memory content update instruction circuit of the embodiment of FIG. 1, and FIG. 3 is a memory of the embodiment of FIG. FIG. 4 is a circuit diagram showing details of the address signal generation circuit, and FIG. 4 is a timing chart showing the operation of the memory content update instruction circuit of FIG. 2 and the memory address signal generation circuit of FIG. 1 ... clock generation circuit, 2 ... power-on control circuit, 3
... A memory content update instructing circuit, 4... A memory address signal generating circuit, 5... A cumulative operating time display circuit, 6... A memory circuit.

Claims (2)

(57) [Claims] A power-on control circuit for generating a power-on signal when the power is turned on; a clock generating circuit for generating first and second clock signals; The second clock signal is input, and the value of the counter is sequentially incremented from 0 by the second clock signal until the memory read data changes from 1 to 0, and then incremented by the count-up signal at regular time intervals. A memory address signal generating circuit for outputting as a memory address signal, and being reset by the power-on signal, counting the first clock signal by a counter, and outputting a memory write instruction signal and the count-up signal every predetermined time. A memory content update instruction circuit and the memory address signal A rewritable type provided in a head disk assembly in which the content stored at a specified address is output as memory read data and the content of the address specified by the memory address signal is set to 1 when the memory write instruction signal is input. A memory circuit for writing 1 to the read-only memory in the direction of a higher address every predetermined time, and an operation integration time display circuit for inputting the memory address signal and displaying the content as an operation integration time. Characteristic magnetic disk drive. 2. A power-on control circuit for generating a power-on signal when the power is turned on, a clock generation circuit for generating first and second clock signals, and the first power-on signal reset by the power-on signal. And a counter value which is sequentially incremented from 0 by the second clock signal until the memory read data changes from 1 to 0 upon input of the second clock signal, and thereafter incremented by a count-up signal at regular time intervals. And a memory address signal generating circuit for outputting a memory write instruction signal and the count-up signal reset by the power-on signal, counting the first clock signal by a counter, and outputting a memory write instruction signal every predetermined time. A memory content update instruction circuit, When the memory write instruction signal is input, the contents of the address specified by the memory address signal are set to 1 and the contents stored in the head disk assembly are rewritten. A memory circuit for writing 1 to the possible read only memory in the direction of a higher address every predetermined time, and an operation integration time display circuit for inputting the memory address signal and displaying the content as an operation integration time. A counter which is incremented by inputting the power-on signal to a reset terminal via an inverter and an OR gate and resetting the first clock signal to a clock terminal;
A decoder that decodes an output signal of the counter and sets the output signal to 1 when the value reaches a predetermined value;
A first D-type flip-flop which is set by the second clock signal and whose output signal becomes 1, and a second D-type flip-flop which is set one clock after the second clock signal and whose output signal becomes 1 A type flip-flop, ANDing each of output signals of the first and second D-type flip-flops with the first clock signal, and outputting the result as the memory write instruction signal and the count-up signal, respectively. A first and second AND gate, wherein the counter is reset via the OR gate when the output signal of the first D-type flip-flop becomes 1. Disk device.