JPS595880B2 - Electronic clock with electrochromic display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece equipped with an electrochromic display device, which includes two or more different drive circuits.

This type of electrochromic display device (hereinafter referred to as EC).

) The drive circuit has an overwhelming number of elements such as display gates. In particular, EC has a memory effect, but is inferior in terms of power consumption. Therefore, it is necessary to apply a signal with a small pulse width and a long period to the display segment. Furthermore, when writing or erasing an EC, it is necessary to apply a low-level or high-level signal to the display segment side with respect to the potential of the common segment, and the number of elements is inevitably increased to generate these signals. This is because it increases. Conventionally, as a method for driving an EC, a signal is applied to a segment only when a segment signal from a tecoder is erased from a write state or written from an erased state.

Although this method (hereinafter referred to as method A) is superior in terms of power consumption, this method requires a large number of IC elements. Another method is to consider the limit of the EC's memory time regardless of the display state, and apply a constant signal to the segment using a pulse signal with a constant period, regardless of changes in the segment signal from the decoder. There is a method.

Although it is possible to reduce the number of elements in this method (hereinafter referred to as method B), it does not show a satisfactory value in terms of power consumption because a constant signal is always applied regardless of the display state. The present invention takes advantage of the characteristics of such a drive method, adopts the above-mentioned method A as a drive method for display digits whose display changes frequently, and puts emphasis on saving power consumption. Ta.

Furthermore, for display digits whose display changes do not occur frequently, the B method, which saves the number of elements, is adopted.
It is an object of the present invention to provide a practical EC display electronic timepiece with a small number of elements and low power consumption. This will be explained below with reference to the drawings.

FIG. 1 is a diagram showing one configuration of the present invention.

In the figure, 1 is a crystal oscillation circuit, 2 is a frequency dividing circuit, and 3 is a clock circuit, which are divided into a front stage 31 and a rear stage 32. The front stage 31 is a display digit clock circuit in which the display digit changes at a fast cycle, and the rear stage 32 is a display digit clock circuit in which the display digit display changes at a slow cycle. Furthermore, 4 is a drive circuit including a decoder circuit,
The front stage 41 is a drive circuit based on the A method described above, and the clock circuit 31
The output 310 of the clock circuit 32 is applied to the latter stage 42, and the output 320 of the clock circuit 32 is applied to the subsequent stage 42, which is a drive circuit based on the B method described above. 5 is an EC display device.

In addition, 6 in the figure takes in an arbitrary frequency from the frequency divider circuit 2,
This circuit generates a signal with a small duty ratio, and its output 8 is applied to a drive circuit 42.

Furthermore, an arbitrary frequency of the output 7 of the frequency dividing circuit 2 is applied to the drive circuit 41 . In this figure, an oscillation signal from an oscillation circuit 1 is frequency-divided by a frequency divider circuit 2, and the frequency-divided signal is applied to a timer circuit 3. The clock signal 310 clocked by the front stage 31 in the clock circuit 3 and the signal 7 sent from the frequency divider circuit 2 are applied to the 1 drive circuit 41 adopting the A method, and the drive circuit 4
The circuit that drives the EC display device 5 with the EC display drive signal generated in step 1 and the signal sent from the front stage 31 in the clock circuit 3 are further clocked in the rear stage 32, and the clock circuit 32 clocks the signal. The clock signal 320 and the signal sent from the frequency dividing circuit 2 are converted into a signal 8 with a small duty ratio by a circuit 6,
This signal 8 and the clock signal 320 are applied to a drive circuit 42 adopting the B method, and the EC display device 5 is driven with the EC display drive signal generated by this drive circuit 42. FIG. 2 shows a circuit according to an embodiment of the present invention.

The drive circuit 41 in Fig. 2 is a drive circuit for display digits in which display digits change at a fast cycle using method A described above.
The output 310 from the clock circuit 31 is applied to the input 1N of the decoder 411 in the clock circuit 31. Furthermore, the decoder 411
Regarding the output A of the latch 412, the output A is the output A of the latch 412.
, and also connected to the input of gate 413 and the negative input of gate 415. Also, the output 7 from the frequency divider circuit 2 is connected to the φ1 input of the latch 412, and also to the φ1 input of the other latch 412. connected to the input. These latches are triggered at the rising edge of the clock,
The QtcD signal is an inverted signal of QiCD. Additionally, the output Q1 of latch 412 is connected to one input of gate 414, and the output Q1 is connected to the other input of gate 415. Furthermore, the output of gate 413 is
connected to the other input of 4. The output of gate 414 goes to the control input of switch 416, gate 415
The outputs of are respectively connected to the control inputs of switch 417. The input of switch 416 is connected to + potential (hereinafter referred to as H level), and the input of switch 417 is connected to one potential (hereinafter referred to as L level).
Furthermore, the output ends of switches 416 and 417 are connected to each other and to segment A (hereinafter referred to as SA). The switches 416 and 417 are electronic switches that turn ON when the control input is at (present) level, and output the input data to the output. Further, the common segment M is connected to GND (hereinafter referred to as 0 level). Furthermore, the same applies to outputs B, C, etc. of the decoder 411. Each display segment is an EC display device in which the display segment is erased by applying an H level and written by applying an L level. To explain the operation of this circuit, assuming that the output A of the decoder 411 maintains the L level, the output Q1 of the latch 412 will be L, .
Since ζ1 is at H level and output A is at L level, the outputs of gates 414 and 415 are at L level, switches 416 and 417 are both in the 0FF state, and S
No potential is applied to A, and SA maintains its previous state.

Next, when the output A of the decoder 411 changes from L to H level, the inputs of the gate 415 both become H level, and the output becomes H.
is output, switch 417 becomes ON, L level is applied to SA, and SA is written.

Furthermore, since both inputs of the gate 414 are at L level, the output of the gate 414 is at L level, and the switch 416 maintains the OFF state. This condition continues until latch 412 is triggered by the clock, at which time Q
1 is H. Ql becomes L level, the output of gate 415 changes from H level to L level, and switch 417 becomes 0FF.
At this time, since L is applied to the input of the gate 414 due to the inverted signal of the output A, the output continues to be at the L level, and the switch 416 maintains the OFF state. This causes SA to maintain the write state as long as output A does not change. Next, when the output A of the decoder 411 changes from H to L level, the inputs of the gate 414 both become H and the H level is output, and the switch 416 becomes 0N, and the SA&
C. H level is applied and SA is erased.

In addition, since both inputs of the gate 415 are at L level, L
The level is output and the switch 417 continues in the 0FF state. This condition continues until latch 412 is triggered by the clock, and when latch 412 is triggered, Q1
is L,. Ql becomes H level, the output of gate 414 changes from H level to L level, and switch 416 becomes 0FF. At this time, since the L level of the A output is applied to the input of the gate 415, the output of the gate 415 maintains the L level, and the switch 417 continues to be OFF. Again, as long as the output A does not change, SA maintains the erased state. The circuit employing the A method has been described above, and next, the circuit using the B method used for display digits whose display changes do not occur very frequently will be explained.

The drive circuit 42 in FIG. 2 is a circuit using the B method.
In the figure, 421 is a display decoder, and the output 320 of the clock circuit 32 is applied to IN'. Further, the signal produced in FIG. 1 and having a constant period and a small duty ratio is applied to one input of gates 423 and 424, and is also applied to one input of the other two-input AND gate. Further, the period of this signal is the same as or 1/2n shorter than the period in which the display of the display digits changes.
Output A' of decoder 421 is connected to the other input of gate 422 and gate 424. The output of gate 422 is connected to the other input of gate 423. The output of gate 423 goes to the control input of switch 425.
The outputs of gates 424 are each connected to control inputs of switches 426. Further, the input of switch 425 is connected to H level, the input of switch 426 is connected to L level, and the output ends of switches 425 and 426 are connected to each other and to segment A' (hereinafter referred to as SN). The switches 425 and 426 are electronic switches that turn ON when an H level is applied to their control inputs. Further, the common segment M' is connected to the O level. To explain the operation of this circuit, when the output A' of the decoder 421 is at L level, the output of the gate 424 always outputs L regardless of the signal 8, and the switch 42
6 is in the 0FF state. Furthermore, when the signal 8 is at H level, the gate 423 outputs H level because both inputs become H level, switch 425 becomes ON, and an H level potential is applied to SA', thereby erasing SA'. Further, when the output A/ of the decoder 421 is at H level, the output of the gate 423 always outputs L regardless of the signal 8, and the switch 42
5 becomes 0FF. Further, the gate 424 is connected to the signal 8 when the signal 8 is high.
When the input signal is at the high level, both inputs become H, so the switch 426 is turned ON at this time, an L level potential is applied to SA5, and SA' is written. In this way, this circuit is driven by the output of the decoder 421 and the signal 8, so when the cycle in which the display of the display digit changes is the same as the cycle of the signal 8, the display of the display digit changes. A signal is applied to each display segment every period,
Furthermore, if signal 8 is 1/2n periods shorter, the signal is applied to 2n circuit display segments.

As a result, in the B method, the drive circuit always sends a signal to each display segment at the same cycle regardless of the display state of each display segment. Further, the signal 8 applied to this circuit is a signal having the same cycle for all display digits, or a signal having the same cycle as the cycle at which the display of the display digits changes. As shown above, method A is used for display digits whose display digits change frequently, as it is superior in terms of power consumption due to the number of elements, and method A is used for display digits whose display digits do not change frequently. adopted method B with a reduced number of elements.

As a result, we were able to complete a practical EC display device drive circuit that has fewer elements than conventional circuits and is far superior in terms of power consumption. In addition, FIG. 3a shows a timing chart of method A according to an embodiment of the present invention, and FIG. 3b shows a timing chart of method B.
1 represents the cycle in which the display of the display digits changes.

Furthermore, T2 in b similarly represents the period in which the display of the display digits changes. Furthermore, FIGS. 4a to 4c show an example in which drive circuits of the A method and the B method are divided by display digits.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the present invention, FIG. 2 is a diagram of an embodiment of the present invention, FIG. 3 a is a timing chart using method A,
Figure 3b is a timing chart using method B.
Figures a to c are examples of type A and type B drive circuits divided by display digits. 4... Drive circuit including a decoder circuit, 41...
...Drive circuit adopting method A, 42...Drive circuit adopting method B, 5...Electrochromics display device, 411,421...For display Decoder, 412... Latch, 413, 422...
...Inverter, 414, 415, 423, 424
・・・・・・2 input AND gate, 416, 417, 4
25,426...Electronic switch.

Claims (1)

[Claims] 1. In an electronic watch that displays a plurality of pieces of time information using an electrochromic display device and a drive circuit that drives the same, the display device has a first display that displays time information whose display contents change at a relatively fast cycle. and a second display section that displays time information whose display contents change at a relatively slow cycle, and the drive circuit is configured to display a display signal that is different from a previous display signal among the display signals periodically output from the decoder. A first type drive circuit applies a write or erase voltage only to the segment corresponding to the signal, and a second type drive circuit applies a write or erase voltage to all segments based on the display signal periodically output from the decoder. the first display section is driven by the drive circuit of the first method, and the second display section is driven by the drive circuit of the second method. An electronic clock with an electrochromic display device.