JPH02234076A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To display a history of over-voltage impressed even after recovering to a normal value by providing a programable memory transistor storing the abnormal over-voltage impressed on a power source electrode and a light emitting element displaying the stored information. CONSTITUTION:The N-channel programable MOS memory transistor Tr Q1 with a floating gate system, N-channel enhancement type MOS Trs Q2, Q5, Q7, and N-channel depression type MOS Trs Q3, Q4, Q6 are provided. When the abnormal over-voltage (larger than +10V, longer than 10musec) is impressed on the power source pole 1 then the condition impressed with the power source voltage (+5V) for the normal operating time is recovered after that, the Tr Q1 is in the OFF condition since electrons are injected into (written in) the floating gate. So, a point A for an output part of the Tr Q2 is made to be an L-level, consequently a point B for the output part of the Tr Q7 is also made to be the L-level; therefore, a current is made to flow in an LED D to put on the lamp. That is, an existence of the history for the electrode 1 impressed with the over-voltage can be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a circuit for storing and displaying an abnormality in a power supply voltage supplied to a power supply electrode of a semiconductor integrated circuit device.

[Conventional technology]

Conventional semiconductor integrated circuit devices (hereinafter referred to as I.C.) did not have a function to automatically store and display abnormalities in the power supply voltage. [Problem to be solved by the invention] The above-mentioned conventional I. C. In this case, when an overvoltage exceeding the operable range is applied to the power supply electrode, the I. C. may malfunction, or the I. C. The internal transistor is destroyed, but is the malfunction or destruction caused by the abnormal overvoltage applied to the power supply electrode?■. C. There was a drawback in that it was impossible to determine whether it was an internal defect that had been present since the time of manufacture after the power supply voltage returned to normal.

[Means to solve the problem]

The semiconductor integrated circuit device according to the present invention is capable of handling an abnormal overvoltage applied to a power supply electrode. It has a programmable memory transistor for storing information, a control circuit and a light emitting element for reading out and displaying the stored information.

Therefore, the history of abnormal overvoltage applied to the power supply electrode is C. The device itself automatically stores information, and even after the power supply voltage applied to the power supply electrodes returns to its normal value, it is possible to display the history of abnormal overvoltage application based on the above-mentioned memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention in an N-channel MOS type semiconductor integrated circuit device.

Q1 is a floating gate type N-channel programmable MOS memory transistor; Q2, Q5, and Q7 are N-channel enhancement type MOS} transistors; Q3, Q4, and Q6 are N-channel depletion type MOS} transistors; D is a light emitting diode;
R is resistance.

In the figure, Q2 and Q3 are always in the NO state during normal operation, and the potential at point A of the output part of Q2 is set to high level when Q1 is ON, and low level when Q1 is OFF. Also, design the characteristics of Q3. still,
Power supply voltage during normal operation is +5V, programmable MOS
The memory transistor Q1 is initially ON, and the power supply electrode 1 has a voltage of +10V or more and a voltage of 10μ. When the above abnormal overvoltage is applied, electrons are injected into the floating gate of the programmable MOS memory transistor Q1, and Q1 is turned off (write characteristic). The circuit operation before the abnormal overvoltage is applied to the power supply electrode 1 is that Q1 is ON, and Q2 and Q3 are also ON, so the potential at point A of the output part of Q2 becomes high level, and Q4
The potential at the output point B of Q7, which has passed through the two-stage inverter consisting of Q5 and Q6 and the inverter Q6 and Q7, is also at a high level, so no current flows through the light emitting diode D. , therefore, the light emitting diode D remains off. Power supply electrode 1 of this circuit that maintains the above state
+IOV or more and 10μ type. If the above abnormal overvoltage is applied and then the power supply electrode 1 returns to the state where the +5V power supply voltage during normal operation is applied, the programmable MoS memory transistor Q1 has electrons injected into the floating gate ( (because writing was performed), it is in the OFF state. If Q1 is OFF, Q
Since the output point A of Q2 becomes low level, and therefore the output point B of Q7 also becomes low level, a current flows through the light emitting diode D, and the light emitting diode D lights up. In other words, it is possible to display that there is a history of abnormal overvoltage being applied to the power supply electrode 1. Note that the resistor R is used to limit the current flowing through the light emitting diode D. Further, in this embodiment, the power supply voltage during normal operation is +5V, and the writing characteristics of the floating gate N-channel programmable MOS memory transistor Q1 are determined by +I applied to the power supply electrode 1.
OV or more and 10μ type. However, the above conditions are I. C. The object of the present invention can be achieved even if the individual operating conditions and writing conditions are set to any desired values.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

This embodiment is an embodiment of a C-MOS semiconductor integrated circuit device, and Q33, Q44, and Q66 are P-channel enhancement type MOS transistors. Floating gate type N-channel four-grammar M
OS memory transistor Ql, N-channel enhancement WMOS transistors Q2 and Q5 and Q7,
The light emitting diode D and the current limiting resistor R are the same as in the first embodiment described above. Before the abnormal overvoltage is applied to the power supply electrode 1, the light emitting diode D is turned off, and after the abnormal overvoltage is applied to the power supply electrode 1, the light emitting diode D is turned off. Each characteristic is designed so that D lights up. In this example, since the two-stage inverter part has a C-MOS structure, the waveform shaping effect is high. Therefore, even if the high-level and low-level potential settings at point A of the output section of Q2 are close to half of the power supply voltage, the waveform shaping effect is high. This has the advantage of being possible. [Effects of the Invention] As explained above, the present invention automatically stores the history of abnormal overvoltage applied to the power supply electrode in a floating gate type programmable memory transistor, so that the voltage applied to the power supply electrode returns to a normal value. There is an advantage that the above abnormality history can be automatically displayed after recovery.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a circuit diagram of another embodiment of the present invention. 1...
・Power supply electrode, Q1...Floating gate N-channel programmable MOS memory transistor, Q2, Q5, Q7...N-channel enhancement ffiMOs} transistor, Q3, Q4,
Q6...N-channel deblessing 3-inch MOS
}Transistor, D... Light emitting diode, R...
...Current limiting resistor, point A...output section of transistor Q2, point B...output section of transistor Q7, Q33, Q44, Q55...P channel enhancement type MOS} transistor. Agent Patent Attorney Susumu Uchihara, Gi

Claims (1)

[Claims] A programmable memory transistor for storing abnormal overvoltage applied to a power supply electrode; and a power supply voltage abnormality history storage and display circuit having a control circuit and a light emitting element for reading and displaying the stored contents of the programmable memory transistor. Features of semiconductor integrated circuit devices.