JP2871329B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit provided with a circuit for preventing electrostatic breakdown of a signal input / output terminal connected to an external circuit.

[0002]

2. Description of the Related Art In recent years, in a MOS type semiconductor integrated circuit, measures against electrostatic destruction have become more important due to miniaturization of elements for realizing high integration.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit in which countermeasures against electrostatic breakdown are taken.

In this circuit, an N-type first MOS transistor T1 having a drain connected to a power supply terminal of a power supply voltage Vcc, a source connected to a signal input terminal TMI, and a gate connected to a reference potential point (ground potential point). , An N-type second MOS transistor T2 having a drain connected to the signal input terminal TMI and a source and a gate connected to the ground potential point, and a resistor R1 having one end connected to the signal input terminal TMI. 1b, and an internal circuit 2 having an input terminal connected to the other end of the resistor R1 and performing a predetermined process on a signal IN input via the resistor R1.

Next, the operation of this circuit will be described.

When a pulse voltage due to static electricity exceeding the breakdown voltage of the MOS transistors T1, T2 is applied to the signal input terminal TMI, the MOS transistors T1, T2
T2 is in a snapback state, and the signal input terminal TMI
Is connected to the power supply terminal and the ground potential point with a low resistance, and discharges the pulse voltage to the power supply terminal and the ground potential point. Therefore, the potential of the input terminal of the internal circuit 2 due to the pulse voltage becomes sufficiently low, and it is possible to prevent the internal circuit 2 and the like from being damaged by static electricity.

[0007] A normal input signal (I
N) is applied, the MOS transistors T1,
Since only a voltage equal to or lower than the breakdown voltage is applied to T2, it is in a non-conductive state, and the potential at the input terminal of the internal circuit 2 is substantially the same as the signal input terminal TMI.

The substrates of the MOS transistors T1 and T2 are normally biased to a negative potential.

[0009]

In this conventional semiconductor integrated circuit, the substrates of the MOS transistors T1 and T2 of the electrostatic discharge protection circuit 1b connected to the signal input terminal TMI are normally biased to a negative potential. In the operating state of
When an undershoot of a negative potential exceeding the threshold value of the MOS transistor T1 occurs in the input signal IN, the MOS
When an impact ionization current flows through the transistor T1 and the internal circuit 2 includes a one-transistor / one-capacitor type memory cell, there is a problem that data stored in the memory cell is destroyed.

An object of the present invention is to prevent the impact ionization current from flowing through the MOS transistor even if the input signal has a negative potential exceeding the threshold of the MOS transistor, thereby destroying the data stored in the memory cell of the internal circuit. There is no need to provide a semiconductor integrated circuit.

[0011]

A semiconductor integrated circuit according to the present invention has a first MOS transistor having a drain connected to a power supply terminal and a source connected to a signal input / output terminal, and a drain connected to the signal input / output terminal. A second MOS transistor having a source and a gate connected to the reference potential point, a third MOS transistor having a drain connected to the gate of the first MOS transistor, a source connected to the signal input / output terminal, and a gate connected to the reference potential point; MOS transistor, an electrostatic discharge protection circuit including a resistance element connected between the drain of the third MOS transistor and the reference potential point, and an internal circuit connected to the signal input / output terminal. doing.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, the drain is connected to the power supply voltage Vcc.
, A source connected to the signal input terminal TMI, an N-type first MOS transistor T1, a drain connected to the signal input terminal TMI, and a source and a gate connected to a reference potential point (ground potential point). N-type second MOS
An N-type third MOS transistor having a transistor T23 drain connected to the gate of the first MOS transistor T1, a source connected to the signal input terminal TMI, and a gate connected to the ground potential point.
An electrostatic discharge protection circuit 1 including an S transistor T3, a resistor R1 having one end connected to the signal input terminal TMI, and a resistor R2 connected between the drain of the third MOS transistor T3 and a ground potential point; It has an internal circuit 2 connected to the signal input terminal TMI via R1.

Next, the operation of this embodiment will be described.

When a pulse voltage due to static electricity exceeding the breakdown voltage of the MOS transistors T1 and T2 is applied to the signal input terminal TMI, and when the normal input signal I
The operation when N is applied is similar to that of the conventional example shown in FIG. 3, and has the same effect.

Here, in a normal operation state, when an undershoot of a negative potential exceeding the threshold value of the MOS transistors T1 and T3 occurs in the input signal IN, the MOS transistor T3 is turned on, so that the MOS transistor T1 is turned on.
Is almost 0 V, and the MOS transistor T1 remains off. That is, no impact ionization current is generated. Therefore, even if the internal circuit 2 includes a one-transistor, one-capacitor type memory cell, the data stored in the memory cell is not destroyed.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, an electrostatic discharge protection circuit 1a is provided on the signal output terminal TMO side of the internal circuit 2.
The basic operation and effects are the same as those of the first embodiment, and further description will be omitted.

In these embodiments, the resistor R2 can be replaced by a transistor.

[0021]

As described above, the present invention provides the first M
A third MOS transistor having a gate connected to a reference potential point is provided between the gate and source of the OS transistor, and a resistance element is provided between the gate and the reference potential point of the first MOS transistor. Even if an undershoot of a negative potential exceeding the threshold value of these MOS transistors occurs in the input signal in a normal operation state, the third MOS transistor is turned on and the first MOS transistor is turned off. There is an effect that an impact ionization current can be prevented from flowing through the first MOS transistor, and destruction of data stored in a memory cell of the internal circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 1a, 1b Electrostatic discharge prevention circuit 2 Internal circuit R1, R2 Resistance T1 to T3 MOS transistor TMI signal input terminal TMO signal output terminal

Claims (2)

(57) [Claims] 1. A first MOS transistor having a drain connected to a power supply terminal and a source connected to a signal input / output terminal, a second MOS transistor having a drain connected to the signal input / output terminal, and a source and a gate connected to a reference potential point. A third MOS transistor having a drain connected to the gate of the first MOS transistor, a source connected to the signal input / output terminal, and a gate connected to the reference potential point;
An electrostatic discharge protection circuit including a resistance element connected between the drain of the third MOS transistor and the reference potential point; and an internal circuit connected to the signal input / output terminal. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the resistance element is formed by a transistor.