JPH06140897A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform a static electricity protecting countermeasure with smaller number of circuit element by providing a transistor where either of a source and a drain is connected to an output terminal, the other is connected to a power source potential point and a gate is connected to a grounded potential point. CONSTITUTION:The transistor TrQ2 is turned off in a normal operation state since the gate is the grounded potential. When high potential static electricity is impressed to the output terminal TM, the static electricity is discharged to the power source potential Vcc 1 point and the grounded potential point GND throug TrQ1 and Q2 and these potential fluctuations of these become same. Thus, the distruction of the circuit element by the static electricity is prevented and the occurrence of a malfunction is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit in which a data output circuit is constructed by an open drain system.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional semiconductor integrated circuit of this type. The semiconductor integrated circuit 1b of this example includes a transistor Q1 whose source is connected to the ground potential point GND, whose drain is connected to the output terminal TM, and whose gate receives the signal IS from the internal circuit. Is connected, and the load resistance R1 of the transistor Q1 in the external circuit 2 is connected to form an open drain type output circuit.

Here, a static electricity protection measure (hereinafter referred to as an ESD measure) of the semiconductor integrated circuit 1b will be described.

In this semiconductor integrated circuit 1b, when static electricity having a high potential of about 2000 V is applied to the output terminal TM, this static electricity is discharged to the ground potential point GND through the transistor Q1. Therefore, the circuit element connected to the output terminal TM can be protected, but the ground potential point GND may be partially momentarily increased by the discharge of the static electricity, and the circuit element in the other portion is destroyed. May occur, or malfunction may occur even if it is not destroyed.

FIG. 4 shows an example of a semiconductor integrated circuit provided with an ESD countermeasure capable of preventing the destruction and malfunction of such circuit elements.

This semiconductor integrated circuit 1c has a source connected to a ground potential point GND, a drain connected to an output terminal TM, a gate connected to a first transistor Q1 for receiving a signal IS from an internal circuit, and a source connected to an output terminal TM. The second transistor Q2 connected to the drain receives the power supply potential Vcc1 and receives the inverted signal ISb of the signal IS from the internal circuit at the gate, the source connected to the output terminal TM, and the drain connected to the gate of the transistor Q2. And a third transistor Q3 having a gate connected to the ground potential point GND.

The transistor Q2 is a load element of the transistor Q1. Therefore, this output circuit is not of open drain type.

However, when a high-potential static electricity is applied to the output terminal TM, this static electricity is generated by the transistors Q1 and Q2.
Since it is discharged to both the power supply potential Vcc1 point and the ground potential point GND through the, the partial instantaneous fluctuation of the potential is because the power supply potential Vcc1 point and the ground potential point GND both have the same fluctuation at the same time. It is possible to prevent the circuit element from being broken and prevent the malfunction.

When a negative potential lower than the threshold voltage Vt of the transistor (with Vcc1 as a positive potential) is applied to the output terminal TM, the transistor Q2 becomes conductive without the transistor Q3, and the power supply potential Vcc1 point and the TM. A defect occurs due to a short circuit with the input circuit of the external circuit to be connected, but if there is the transistor Q3, this transistor Q3 is short-circuited and the transistor Q2 is opened. .

[0010]

In the above-described conventional semiconductor integrated circuit 1b of the first example, since there is no electrostatic discharge path from the output terminal TM to the power supply potential point, the ESD countermeasure is insufficient and the partial There is a risk that circuit elements may be destroyed or malfunction may occur in the semiconductor integrated circuit 1c of the second example.
There is a drawback in that the number of upper circuit elements that are not open drain type output circuits increases.

An object of the present invention is that the number of circuit elements is small and E
An object of the present invention is to provide a semiconductor integrated circuit of an output circuit of an open drain system which can sufficiently take SD measures.

[0012]

A semiconductor integrated circuit of the present invention comprises a first transistor having a source connected to a ground potential point, a drain connected to an output terminal, a gate for receiving a signal from an internal circuit, and a source and a drain. A second transistor, one of which is connected to the output terminal, the other of the source and drain is connected to a power supply potential point, and the gate is connected to the ground potential point.

The gate of the second transistor is connected to the substrate potential point.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor integrated circuit shown in FIG. 3 in that one of the source and the drain is connected to the output terminal TM and the other of the source and the drain is connected to the power supply potential Vcc1 point. Is provided at a point where a transistor Q2 is connected to the ground potential point GND.

Next, the operation of this embodiment will be described.

In normal operation, the transistor Q2 is
Since its gate is at the ground potential, it is in the off state, and the circuit is the same as that of the conventional example of FIG.

Next, when a high-potential static electricity is applied to the output terminal TM, this static electricity is discharged to the power supply potential Vcc1 point and the ground potential point GND through the transistors Q1 and Q2, and these potential fluctuations are the same. Therefore, it is possible to prevent the circuit element from being damaged by the static electricity and prevent the malfunction.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the gate of the transistor Q1 in the first embodiment is connected to the substrate potential Vbb point.

In the first embodiment, when the potential of the output terminal TM becomes a negative potential lower than the threshold voltage Vt of the transistor (Vcc1 is a positive potential), the transistor Q2 becomes conductive and the input circuit of the external circuit 2 is turned on. Is short-circuited with the power supply potential Vcc1 point. In this second example, the transistor Q
Since the gate of 2 is normally at the substrate potential Vbb of a negative potential, the transistor Q2 does not conduct even when a negative potential lower than the threshold voltage Vt is applied to the output terminal TM, and therefore the power supply potential Vcc1 point and the external circuit. A short circuit with the second input circuit can be prevented.

[0023]

As described above, according to the present invention, the source,
One of the drain is connected to the output terminal, the other of the source and the drain is connected to the power supply potential point, and the gate is connected to the connection potential point or the substrate potential point. Since the high-potential static electricity is discharged to the power supply potential point and the ground potential point via the first and second transistors, the potential fluctuations at the power supply potential point and the ground potential point are the same, and the circuit element is destroyed. Is effective in preventing the occurrence of malfunctions and malfunctions.
By setting the gate of the transistor of to the substrate potential,
There is an effect that it is possible to prevent a short circuit between the input circuit of the external circuit and the power supply potential point with a smaller number of circuit elements than in the conventional example (second example).

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a first example of a conventional semiconductor integrated circuit.

FIG. 4 is a circuit diagram of a second example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 1a to 1c Semiconductor integrated circuit 2 External circuit Q1 to Q3 Transistor

Claims (2)

[Claims] 1. A first transistor having a source connected to a ground potential point, a drain connected to an output terminal and a gate receiving a signal from an internal circuit, and one of a source and a drain connected to the output terminal. A second one of which the other of the drains is connected to the power supply potential point and the gate is connected to the ground potential point
A semiconductor integrated circuit comprising: 2. The semiconductor integrated circuit according to claim 1, wherein the gate of the second transistor is connected to the substrate potential point.