JPH0467384A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To easily detect not just energizing time but time when a head disk assembly actually operates by providing a rewritable read-only memory in the head disk assembly and adding data whenever prescribed time elapses. CONSTITUTION:A memory address signal generation circuit 4 is reset by a power supply signal 9 and a memory address signal 12 is increased until memory read data 13 is changed. A memory content update instruction circuit 3 is reset by the power supply signal 9 and outputs a memory write instruction signal 11 and a count up signal 10 whenever prescribed time elapses. A memory circuit 6 outputs a content stored in an address which the memory address signal 12 designates and sets the content of the designated address to '1' when the memory write instruction signal 11 is inputted from the memory content alteration instruction circuit 3. An operation integrated time display circuit 5 displays the memory address signal 12 as operation integrated time. Thus, time when the head disk assembly is actually used can accurately be learnt.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device used as a data storage device in an information processing device.

[Conventional technology]

Magnetic disk drives used as data storage devices in information processing equipment have traditionally been used as auxiliary external storage devices, so their operating time is not necessarily long and their service life ends within a short period of time (for example, 2 to 3 years). Since there were few problems caused by frequent failures due to this, few games were equipped with a measuring device for accumulating operating time, and those that were equipped with a measuring device were unable to calculate the accumulating time of input power supply. Is going.

[Problem to be solved by the invention]

In recent years, magnetic disk devices have come to be used for online databases, and information processing devices themselves are often used 24 hours a day without interruption. The mechanical part that moves the head to a designated position on the magnetic disk is housed in a sealed container).Replace the magnetic disk periodically due to deterioration of the magnetic disk rotation mechanism, dirt on the magnetic disk or the magnetic head, etc. As a guideline for this purpose, it has become necessary to accurately know the amount of time that the head disk assembly (HDA) was actually used.

The problem to be solved by the present invention, in other words, the purpose of the present invention is to meet the above-mentioned demands for a magnetic disk device, to easily know the time when an HDA is actually used, and to do so at a low price. An object of the present invention is to provide a magnetic disk device equipped with a highly reliable cumulative operating time measuring circuit.

[Means to solve the problem]

A magnetic disk device of the present invention includes a power-on control circuit that generates a power-on signal when the power is turned on, and a clock generation circuit that generates first and second clock signals.
The memory read data is reset by the power-on signal and the first and second clock signals are input.
a memory address signal generation circuit that outputs, as a memory address signal, a counter value that is sequentially incremented from 0 by the second clock signal until the value changes from 0 to 0, and thereafter incremented by a count-up signal at regular intervals; a memory content update instruction circuit that is reset by a power-on signal, counts the first clock signal by a counter, and outputs a memory write instruction signal and the count-up signal every predetermined period of time; A rewritable read-only device provided within the head disk assembly, which outputs the contents stored at the address specified as memory read data, and when the memory write instruction signal is input, the contents of the address specified by the memory address signal are set as 1. It is equipped with a memory circuit that writes 1 into the memory in the direction of a higher address every predetermined period of time, and a cumulative operating time display circuit that inputs the memory address signal and displays the contents as cumulative operating time. , a counter that is reset by a memory content update instruction circuit inputting the power-on signal to a reset terminal via an inverter and an OR gate and incremented by inputting the first clock signal to a clock terminal; and an output signal of the counter. a decoder whose output signal becomes 1 when the value becomes a predetermined value, and a first D whose output signal becomes 1 when set by the second clock signal.
a second D-type flip 70 whose output signal is set to 1 after one clock of the second clock signal; and the first and second D-type flip 70. first and second AND gates that perform a logical product of each of the output signals and the first clock signal and output the result as the memory write instruction signal and the count up signal, respectively; When the output signal of the type flip 70 becomes 1, the counter is reset to a small value via the OR gate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, when the power is turned on, a power-on control circuit 2 generates a power-on signal 9 that is used to reset each circuit when the power is turned on. The clock generation circuit 1 is
Phase clock signals 7 and 8 are generated. The memory address signal generation circuit 4 inputs the power-on signal 9 from the power-on control circuit 2 and the clock signals 7 and 8 from the clock generation circuit 1, is reset by the power-on signal 9, and outputs the memory read from the memory circuit 6. The value of the counter that is sequentially incremented from 0 by the clock signal 8 until the read data 13 changes from "l" to "0" is output as the memory address signal 12. The clock signal 7 is counted by a counter and a memory write instruction signal 11 and a count-up signal 10 are output every predetermined time period (for example, every hour).The memory circuit 6 receives input from the memory address signal generation circuit 4. The content stored at the address specified by the memory address signal 12 is output as memory read data 13, and when the memory write instruction signal 11 is input from the memory content update instruction circuit 3, the content stored at the address specified by the memory address signal 12 is output. The content of the address is set to 1. The cumulative operating time display circuit 5 receives the memory address signal 12 and displays the content as the cumulative operating time using a display means such as a light emitting diode.

FIG. 2 is a circuit diagram showing details of the memory content update instruction circuit of the embodiment shown in FIG. 1, and FIG. 4 shows the operation of the memory content update instruction circuit of FIG. 2 and the memory address signal generation circuit of FIG. 3. This is a timing chart.

In FIGS. 2 and 4, the power-on signal 9 is input to the reset terminal of the counter 21 via the inverter 27 and the OR gate 28, so the value of the counter 21 is 0 when the power is turned on. The clock signal 7 is input to one clock terminal of the counter 21, and the counter 21 is incremented every time the clock signal 7 is input. The output signal 31 of the counter 21 is decoded by the decoder 22, and when the value reaches 3600, the output signal 31 is decoded by the decoder 22.
2 becomes 1, the D-tie 1 flip 70 knob 23 is set by the clock signal 8, and its output signal 33 becomes 1. Furthermore, one clock after clock signal 8, D
Type 7 gamma flop 24 is set and its output signal 34 becomes one. Output signals 33 and 34 are connected to clock signal 7 in AND gates 25 and 26, respectively.
and the memory write instruction signal 1, respectively.
1 and a count-up signal 10. Furthermore, when the output signal 33 becomes 1, the counter 21 is reset via the OR gate 28.

FIG. 3 is a circuit diagram showing details of the memory address signal generation circuit of the embodiment shown in FIG. 1, and FIG. 4 is a timing chart showing the operation of the memory content update instruction circuit of FIG. 2.

In FIGS. 3 and 4, power-on signal 9 is inputted to the reset terminals of D-type flip-flops 45, 46, and 48 via inverter 49 to initialize each D-type flip-flop 70. Since the power supply voltage ■ is applied to the D terminal of the D type flip 70 knob 45 and becomes 1, when the power supply voltage 9 becomes 1 and the clock signal 7 that is first output is input, the D type Clip-flop 45 is set and its output signal 55 becomes 1. Since the output signal 55 is input to the D terminal of the D type clip flop 46, the output signal 56 of the D type flip 70 tube 46 becomes 1 when the next clock signal 8 is input. , 2, the negative polarity output signal of the D-type flip 70/sol 146 is input to the reset terminal of the counter 44, so that the reset is canceled.

- On the other hand, while the gate of the AND gate 42 is open and the D-type flip 70 knob 41 is 1, a pulse is sent to the clock terminal of the counter 44 via the AND gate 42 and the OR gate 43 at the timing of the clock signal 8. and the counter 44 is incremented.

FIG. 4 shows a case where the memory read data 13 becomes 0 when the memory address signal 12 becomes 3'', and at that point, the memory read data 13 is transferred to the D terminal of the D type flip-flop 41. , Since the clock signal 7 is input to the clock terminal, the D-type flip-flop 41 is reset at the rising edge of the clock signal 7, and the incrementing operation of the counter 44 is interrupted.After that, the memory content update instruction circuit When the count up signal 10 is input from 3, a pulse is applied to the clock terminal of the counter 44 via the OR gate 43,
Counter 44 is incremented.

〔Effect of the invention〕

As explained above, in the magnetic disk drive of the present invention, a rewritable read-only memory is provided in the head disk assembly, and data is added every time a certain period of time has elapsed. This has the effect of making it easy to know the operating time.

[Brief explanation of drawings]

FIG. 1 is a program diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the memory content update instruction circuit of the embodiment of FIG. 1, and FIG. 3 is an embodiment of the embodiment of FIG. 1. FIG. 4 is a timing chart showing the operation of the memory content update instruction circuit of FIG. 2 and the memory address signal generation circuit of FIG. 3. FIG. DESCRIPTION OF SYMBOLS 1...--clock generation circuit, 2...--power-on control circuit, 3...--memory content update instruction circuit, 4
...Memory address signal generation circuit, 5...
- Earning ant calculation time display circuit, 6... Memory circuit.

Claims (1)

[Claims] 1. A power-on control circuit that generates a power-on signal when the power is turned on, a clock generation circuit that generates first and second clock signals, and a clock generator that is reset by the power-on signal. The first and second clock signals are input and the memory read data is sequentially incremented from 0 by the second clock signal until the memory read data changes from 1 to 0, and thereafter it is incremented at regular intervals by the count-up signal. a memory address signal generating circuit that outputs the value of a counter to be read as a memory address signal; and a memory address signal generating circuit that is reset by the power-on signal, counts the first clock signal by the counter, and writes memory every predetermined period of time. a memory content update instruction circuit that outputs an instruction signal and the count-up signal; and a memory content update instruction circuit that outputs content stored at an address specified by the memory address signal as memory read data and inputs the memory write instruction signal. a memory circuit that takes the content of the address specified by the memory address signal as 1 and writes 1 into a rewritable read-only memory provided in the head disk assembly every predetermined period of time in the direction of a higher address; and the memory address; 1. A magnetic disk device comprising: a cumulative operating time display circuit that inputs a signal and displays the content as cumulative operating time. 2. A power-on control circuit that generates a power-on signal when the power is turned on; a clock generation circuit that generates first and second clock signals; The counter value is sequentially incremented from 0 by the second clock signal until the memory read data changes from 1 to 0 by inputting the second clock signal, and thereafter is incremented by the count-up signal at regular intervals. a memory address signal generation circuit that outputs a memory address signal; and a memory address signal generation circuit that is reset by the power-on signal, counts the first clock signal with a counter, and outputs a memory write instruction signal and the count-up signal every predetermined time period. a memory content update instruction circuit, which outputs the content stored at the address specified by the memory address signal as memory read data, and when the memory write instruction signal is input, the content of the address specified by the memory address signal; 1 includes a memory circuit that writes 1 to a rewritable read-only memory provided in the head disk assembly every predetermined period of time in the direction of a higher address; and a memory circuit that inputs the memory address signal and uses the contents as the cumulative operating time. and a memory content update instruction circuit that inputs the power-on signal to a reset terminal via an inverter and an OR gate to be reset, and inputs the first clock signal to a clock terminal to increment the memory content update instruction circuit. a decoder that decodes the output signal of the counter and sets the output signal to 1 when the value reaches a predetermined value; and a decoder that is set by the second clock signal so that the output signal becomes 1.
a first D-type flip-flop whose output signal becomes 1 when set one clock after the second clock signal; and a second D-type flip-flop whose output signal becomes 1; first and second AND gates that perform a logical product of each of the output signals of the flip-flop and the first clock signal and output the result as the memory write instruction signal and the count up signal, respectively; A magnetic disk drive characterized in that the counter is reset via the OR gate when the output signal of one D-type flip-flop becomes 1.