JPH02168598A - Interlock operation order judgement circuit - Google Patents

Abstract

PURPOSE:To know a series of IL(interlock) operational order completely by recording all the IL signals after a first IL signal in a recording means, whose contents are read in order for the judgement. CONSTITUTION:If, for example, an IL signal 13 is generated, it is input to a decoder 1 and the decode output is input to a memory 4. The IL signal 13 drives FF3 via an OR circuit 2 at the same time, and a starting signal is inversed by the output to be counted as 1. A switching circuit 5 switches the connection of the memory 4 with an address input terminal from the side of a CPU 8 to the side of a counter 6, in which clock counting from a clock generator 7 is started by the starting signal 1 of the FF3 at the same time. A light signal is input to a terminal R/inversion W of the memory 4 at the same time, and the IL signal is recorded in the memory 4 in order. When counting up is performed full to the memory capacity by the counter 6, the circuit 5 performs switching, and the contents of the memory 4 are read in order and is input to the CPU 8, for the operational order of the IL to be judged and displayed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an interlock operation order determination circuit that determines the interlock operation order from the generation order of ink-lock signals generated according to a series of operations in a predetermined device such as an accelerator or a nuclear fusion device.

[Conventional technology]

FIG. 2 is a circuit diagram of a conventional interlock operation order determining circuit. In the figure, 2 indicates N interlock signals 11 to IN (
However, the order of generation does not follow the number of this signal) is input to an OR circuit, 3 is a flip-flop as a starting circuit that is inverted by the output signal of this OR circuit 2, and 9 is a flip-flop for the above-mentioned N signals. Interlock signal 11~I
These are AND circuits which are provided corresponding to each of the flip-flops 3 and whose opening/closing is controlled by the output (activation signal) of the flip-flop 3. Next, the operation will be explained. One of the interlocks corresponding to the interlock signals II to IN also operates, and when that interlock signal is generated, the flip-flop 3 is inverted by applying the interlock signal through the OR circuit 2, and its output is becomes a “0”° signal and closes all N AND circuits 9. However, now, for example, assuming that the interlock corresponding to the interlock signal 11 is activated, this interlock signal 11 is transmitted through the corresponding AND circuit 9 that had previously activated the interlock signal 11. , and sent to a CPU (not shown). That is, the operation of the interlock is determined only for the interlock signal (one interlock signal) of the interlock that operates first.

[Problem to be solved by the invention]

Since the conventional interlock operation order determination circuit is configured as described above, it can only determine the first interlock that operates, and therefore cannot know the operation order of other interlocks that follow. There was a problem. However, in recent years, various devices such as accelerators and nuclear fusion have become larger and more complex, and many of them operate in conjunction with each other in the event of an abnormality. Knowing the operating sequence of a series of interlocks that occur in a short period of time is absolutely necessary for failure analysis.
It is desired to realize such an interlock operation order determining circuit. The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide an interlock operation order determining circuit that can know all of a series of interlock operation orders.

[Means to solve the problem]

The interlock operation order determining circuit according to the present invention is activated from the time when the interlock signal of the first activated interlock is generated, and sequentially processes all the interlock signals after the first interlock signal in the order in which they are generated. The information is recorded in the recording means, and the interlock operation order is determined by the determining means from the recorded contents.

[For use]

The recording means in this invention sequentially records all the interlock signals starting with the interlock signal of the interlock that operated first, and then the discriminating means sequentially records the contents recorded in this recording means. Determine the interlock operation order.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a series of N interlock signals 11
~Decoder that inputs and decodes IN, 2 is the above OR
circuit, 3 is the flip-flop, 4 is the decoder l
The interlock signals 1 to 1 are input by inputting the decoded output of
5 is a switching circuit that performs a switching operation in response to a start signal output from the flip-flop 3; 6 counts clocks from a clock generator 7 and stores the count value in the memory 4; A counter 8 controls all operations of the interlock operation order determining circuit of this embodiment shown in FIG. The CPU serves as a determining means. Next, the operation will be explained. For example, if it is assumed that among the N interlocks, the interlock corresponding to the interlock signal 13 is activated, the interlock signal 13 is generated, inputted to the decoder 1 and decoded,
The decoded output is applied to the data input terminal of the memory 4. At the same time, the interlock signal 13 is input to the OR circuit 2 to drive the flip-flop 3, and its output, the activation signal, is inverted to "l", thereby causing the switching circuit 5 to change the address of the memory 4. Switch the connection to the input terminal from the CPO3 side to the counter 6 side. At the same time, the counter 6 is driven by the activation signal "BI" of the flip-flop 3 and starts counting the clock from the clock generator 7. Furthermore, at the same time, a write signal is applied to the input terminal R/W of the memory 4. Therefore, from now on, the count value of the counter 6 is input as an address signal to the address input terminal of the memory 4, and in accordance with the address signal, the interlock signal 13 generated from then on is successively generated. The lock signal is recorded in the memory 4. Next, when the count value of the counter 6 counts up to the capacity of the memory 4, the counter 6 resets the flip-flop 3 by the count-up signal.
Further, the count-up signal is applied to the CPU 8 as an interrupt signal. Then, the switching circuit 5 performs a switching operation by inverting the flip-flop 3, and switches the connection of the address input terminal to the memory 4 to the CPLIB side. In addition, input terminal R/of memory 4
A read signal is given to W. Therefore, from now on, the address signal from the CPU 8 is supplied to the memory 4, and the recorded contents of the memory 4 are sequentially read out.
Sent to cpus. Based on the data indicating the interlock operation state, the CPU 8 pays particular attention to the operation occurrence time of the interlock signal (interlock signal 13 in the present example) of the first interlock that occurs when the interlock operation changes, and calculates a series of data. Determine and process interlock operation order. The determination result is displayed on a display device (not shown) or printed out on a printing device, for example.

【Effect of the invention】

As described above, according to the present invention, the interlock operation order determining circuit is started from the time when the interlock signal of the first operated interlock is generated, and all the interlock signals after the one interlock signal are activated. The interlock signals are sequentially recorded in the recording means in the order in which they occur, and then the recorded contents are read out and the determining means determines the interlock operation order, so it is extremely useful for failure analysis when abnormalities occur in the equipment. It has the effect of demonstrating.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an interlock operation order determining circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional interlock operation order determining circuit. 3 is a flip-flop (starting circuit), 4 is a memory (recording means), and 8 is CPLJ (discriminating means). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1 21!1

Claims (1)

[Claims] Driven by the first interlock signal generated in an interlock operation order determination circuit that determines the interlock operation order from the generation order of interlock signals generated according to a series of operations in a predetermined device such as an accelerator or nuclear fusion device. and a starting circuit that generates a starting signal, and a starting circuit that is started by the starting signal of this starting circuit and said
An interlock characterized by comprising a recording means for sequentially recording all interlock signals after the first interlock signal, and a determining means for determining the interlock operation order from the recorded contents of the recording means. Operation order determination circuit.