JPS6136841A - Input and output device - Google Patents
Input and output deviceInfo
- Publication number
- JPS6136841A JPS6136841A JP15982684A JP15982684A JPS6136841A JP S6136841 A JPS6136841 A JP S6136841A JP 15982684 A JP15982684 A JP 15982684A JP 15982684 A JP15982684 A JP 15982684A JP S6136841 A JPS6136841 A JP S6136841A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- address
- code
- switch
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は操作パネルを有する入出力装置に関するもので
、特にパネル操作の記憶方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an input/output device having an operation panel, and particularly to a storage method for panel operations.
（従来技術）
この種の入出力装置においては障害が発生した場合に、
障害調査のための情報として障害発生に至る迄に行なっ
た操作者のパネル操作手順が重要な要素となる場合があ
るが、従来の入出力装置では障害発生時点だけの情報を
操作パネルに表示している。したがって、障害発生に至
る迄のパネル操作は操作者の記憶に頼らざるを得ず、そ
の為に曖昧な操作手順しかわからないという欠点があっ
た。(Prior art) When a failure occurs in this type of input/output device,
The panel operation procedures performed by the operator leading up to the occurrence of the failure may be an important element as information for fault investigation, but with conventional input/output devices, only the information at the time of the failure is displayed on the operation panel. ing. Therefore, the panel operations up to the occurrence of the failure must rely on the operator's memory, which has the disadvantage that only vague operating procedures are known.
（発明の目的）
本発明の目的は、操作者の行なった操作手順を記憶する
ことにより、上記欠点を解決し、障害発生時点迄の操作
手順を正確に採取することを可能にした入出力装置を提
供することにある。(Object of the Invention) The object of the present invention is to provide an input/output device that solves the above drawbacks by storing the operating procedures performed by the operator, and makes it possible to accurately collect the operating procedures up to the point at which a failure occurs. Our goal is to provide the following.
（発明の構成）
本発明の装置は、操作パネルを有する入出力装置におい
て、前記操作パネルのスイッチを操作する毎に前記スイ
ッチに対応したコードを発生するコード発生回路と、前
記コード発生回路から発生された前記操作コードを格納
する記憶回路と、操作によって前記記憶回路から操作コ
ードを読み出す操作コード続出回路とを設けたことを特
徴とする。(Structure of the Invention) The device of the present invention is an input/output device having an operation panel, and includes a code generation circuit that generates a code corresponding to the switch each time a switch on the operation panel is operated, and a code generated from the code generation circuit. The present invention is characterized in that it is provided with a memory circuit that stores the operation code that has been issued, and an operation code successive circuit that reads out the operation code from the memory circuit in response to an operation.
（実施例）
次に本発明の実施例について図面を参照して詳細に説明
する。(Example) Next, an example of the present invention will be described in detail with reference to the drawings.
本発明の一実施例を示す第１図を参照すると、本実施例
は操作パネル上の３つのスイッチ１，２゜３と、前記ス
イッチ１，２．３が押下された時に発生する各信号ａ、
ｂ、ｃを入力とし各々の信号ａ、ｂ、ｃＫ対応する操作
コードを発生するコード発生回路４と前記操作コードを
格納する記憶回路５と、前記記憶回路５の格納アドレス
を指定するアドレス回路６と、格納アドレスの最上位ア
下レスを記憶する最上位アドレス記憶回路７と、前記ア
ドレス回路６の格納アドレスと前記最上位アドレス記憶
回路７の最上位アドレスとを比較する比較回路８と、操
作コードを読み出すための読出しスイッチ１０と、前記
読出しスイッチ１（ｌ押下時に前記記憶回路５から操作
コードを読出し表示する表示回路９とから構成されてい
る。Referring to FIG. 1 showing one embodiment of the present invention, this embodiment has three switches 1, 2.3 on the operation panel and each signal a generated when the switches 1, 2.3 are pressed. ,
A code generation circuit 4 which receives input signals b and c and generates operation codes corresponding to the signals a, b and cK, a memory circuit 5 which stores the operation codes, and an address circuit 6 which specifies the storage address of the memory circuit 5. , a most significant address storage circuit 7 that stores the most significant address of the stored addresses, a comparison circuit 8 that compares the stored address of the address circuit 6 with the most significant address of the most significant address storage circuit 7, and an operation. It consists of a readout switch 10 for reading out the code, and a display circuit 9 that reads out the operation code from the storage circuit 5 and displays it when the readout switch 1 (l is pressed).
次に本実施例の動作について述べる。Next, the operation of this embodiment will be described.
操作パネル上の、たとえば、スイッチ１が押下されると
信号ａが論理″′ｌ”となり、コード発生回路４の入力
となる。コード発生回路４は信号ａに対応した操作コー
ドを発生し信号線ｅにより記憶回路５に操作コードの格
納指示を出す。When, for example, switch 1 on the operation panel is pressed, signal a becomes logic "'l" and becomes an input to code generation circuit 4. The code generation circuit 4 generates an operation code corresponding to the signal a, and issues an instruction to the storage circuit 5 to store the operation code via the signal line e.
記憶回路５はアドレス回路６により指定されたアドレス
に操作コードを格納する。アドレス回路６は操作コード
が記憶回路５に格納された後に信号線ｄにより＋１され
次の格納アドレスを示す。The memory circuit 5 stores the operation code at the address specified by the address circuit 6. After the operation code is stored in the memory circuit 5, the address circuit 6 is incremented by 1 by the signal line d to indicate the next storage address.
比較回路８は最上位アドレス記憶回路７の最上位アドレ
スとアドレス回路６の格納アドレスとを比較し一致する
ならば、信号線ｆによりアドレス回路６の格納アドレス
を初期値に戻す。Comparison circuit 8 compares the most significant address of most significant address storage circuit 7 with the stored address of address circuit 6, and if they match, returns the stored address of address circuit 6 to its initial value via signal line f.
スイッチ２，３が押下された場合は同様に各々の信号す
、ｃに対応する操作コードが記憶回路５に格納される。When the switches 2 and 3 are pressed, the operation codes corresponding to the respective signals A and C are similarly stored in the memory circuit 5.
操作コード金読出す場合には、読出しスイッチ１０を押
下すると、信号線ｇを介してアドレス回路６の格納アド
レスｅ−ＩＬ、記憶回路５の内容を表示回路９に表示す
る。読出しスイッチ１ｏは押下する毎に−１されるので
記憶回路５に格納された最新の操作コードから順に胱出
すことができる。When reading the operation code money, when the read switch 10 is pressed, the storage address e-IL of the address circuit 6 and the contents of the memory circuit 5 are displayed on the display circuit 9 via the signal line g. Since the readout switch 1o is decremented by 1 each time it is pressed, the operation codes stored in the memory circuit 5 can be read out in order.
（発明の効果）
本発明にはパネル操作手順を記憶回路に記憶することに
より、操作手順が正確に採取できるという効果がある。(Effects of the Invention) The present invention has the advantage that by storing the panel operation procedure in a memory circuit, the operation procedure can be accurately collected.
第１図は本発明の一実施例を示す図でおる。
１．２．３・・・・・・操酢−−−Ｎトａスイッチ、４
・・・・・・コード発生回路、５・・・・・・記憶回路
、６・・・・・・アドレス回路、７・・・・・・最上位
アドレス記憶回路、８・〜・・・・比較回路、９・・・
・・・表示回路、１ｏ・・・・・・読出しスイッチ。
茅 ｌ 図FIG. 1 is a diagram showing an embodiment of the present invention. 1.2.3...Switch--N to a switch, 4
......Code generation circuit, 5...Memory circuit, 6...Address circuit, 7...Most significant address storage circuit, 8...... Comparison circuit, 9...
...Display circuit, 1o...readout switch. Kaya l figure
Claims (1)
ルのスイツチを操作する毎に前記スイツチに対応したコ
ードを発生するコード発生回路と、前記コード発生回路
から発生された前記操作コードを格納する記憶回路と、
前記操作によつて記憶回路から操作コードを読み出す操
作コード読出回路とを設けたことを特徴とする入出力装
置。In an input/output device having an operation panel, a code generation circuit generates a code corresponding to the switch each time a switch on the operation panel is operated, and a storage circuit stores the operation code generated from the code generation circuit. ,
An input/output device comprising: an operation code reading circuit that reads an operation code from a storage circuit according to the operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15982684A JPS6136841A (en) | 1984-07-30 | 1984-07-30 | Input and output device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15982684A JPS6136841A (en) | 1984-07-30 | 1984-07-30 | Input and output device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6136841A true JPS6136841A (en) | 1986-02-21 |
Family
ID=15702091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15982684A Pending JPS6136841A (en) | 1984-07-30 | 1984-07-30 | Input and output device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136841A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63257042A (en) * | 1987-04-14 | 1988-10-24 | Fanuc Ltd | Memory device for history of key operation |
-
1984
- 1984-07-30 JP JP15982684A patent/JPS6136841A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63257042A (en) * | 1987-04-14 | 1988-10-24 | Fanuc Ltd | Memory device for history of key operation |
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