JPS6125167B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device that employs a pipeline control method.

Large-scale electronic computers generally use a so-called pipeline control method in which instruction processing is divided into several parts and each part is processed in parallel by independent subunits. If this pipeline control method is adopted, the average instruction execution time can be brought closer to the processing time of the subunit, and the information processing device as a whole can achieve maximum cost performance.

For convenience, it is assumed here that the instruction processing stage of the processing device is divided into four stages as shown in FIG. In Figure 1, subunit D is responsible for decoding and address modification, subunit A is responsible for converting logical addresses to real addresses, and referencing the buffer storage directory, and subunit L is responsible for reading operands from the storage device (buffer storage or main storage). subunit E represents the execution of an instruction. In a pipeline control type processing device, each of these subunits is an independent subunit, and each instruction is sequentially processed in parallel. In other words, when a subunit finishes processing one instruction, it starts processing the next instruction. A time chart of such processing is shown in FIGS. 2a and 2b. Figure 2 a and b are time charts showing the same thing, with instructions 0 to
4 shows how D, A, L and E are processed.

The factors that determine the instruction execution speed of an information processing device can be roughly divided into three: the frequency of the synchronous clock (referred to as a machine cycle), the access time cycle time of the storage device, and the data width and control method of the logic. In conventional information processing devices, these factors are unique to each machine, so it has been difficult to vary the instruction execution speed, that is, the processing capacity of the information processing device. The few methods that have been implemented are to change the machine cycle in a small range, or to change the capacity of the storage device.
However, the former has the disadvantage of having problems with machine reliability and having a very small variable range. Furthermore, the latter has little effect on the performance of individual programs, and the processing capacity of many programs executed under the control program changes, making it impossible to intentionally control the processing capacity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pipeline information processing device that allows processing capacity to be easily controlled, does not have the above-mentioned drawbacks, and allows fine-grained capacity values to be set.

FIG. 3 shows a state in which instructions are executed by an information processing apparatus implementing the present invention. In the normal mode shown in FIG. 3a, when there is no cause of pipeline disturbance, control is performed so that execution of one instruction is completed in each cycle. On the other hand, when the processing capacity control of the present invention is turned on, FIGS. 3b, 3c, and 3
As shown in FIG. d, the end of execution of an instruction changes depending on each mode. It can be seen that when there are no disturbance factors, mode 1 has a processing capacity of 1/2 of mode 0, mode 2 has a processing capacity of 1/3 of mode 0, and mode 3 has a processing capacity of 1/4 of mode 0. Also normal mode, mode 1, mode 2,
By combining mode 3, it is possible to finely control the performance degradation relative to the normal mode.

Next, an embodiment of the present invention will be described with reference to FIGS. 4, 5, 6, and 7.

The information processing apparatus according to the present invention has a flip-flop corresponding to each subunit to display the status of each subunit. In this state, three flip-flops are provided, and FIG.
It has the meaning shown in , and is in either state at any given time. i is subunit D, A,
Represents L and E, IDL is idle state,
In other words, BSY represents a busy state, that is, a state in which processing ends, and RDY represents a ready state, that is, a state in which processing is started.

Next, the transition diagram of this state is expressed as subunit i (i=
D, A, L, E) are shown as an example in FIG. 4b, and the relationship between subunit i and a specific END signal is shown in FIG. 4c. In FIG. 4c, for example, for subunit D, (i-1) END means the end of the instruction processing in the previous stage of subunit D, that is, (D
-1) subunit does not exist, iEND is DEND, indicating the completion of instruction reading, indicating the end of instruction processing in subunit D, that is, the completion of instruction decoding and address modification, and for subunit A ( i-1) END means the end of instruction processing in subunit D, which is the preceding stage of subunit A, or DEND. Indicates the end of the reference.

In FIG. 4b, in the initial state, each subunit i is in the input waiting state, i.e., iIDL. To explain the state transition using subunit D as an example, in the initial state, DIDL is 1,
DRDY and DBSY are 0. Since the completion of instruction reading corresponds to the (D-1) END condition, the state of DIDL continues on line 1 until instruction reading is completed. When the instruction reading is completed, (D-1) END becomes 1, and the state moves to DRDY on line 2. When the processing ends in the next cycle, DEND becomes 1, and the state changes according to line 3 or line 4. If there is a condition to suppress DEND (Block DEND: BDEND), the state moves to DBSY state at line 5. In the DBSY state, when BDEND is 1, the DBSY state continues at line 6, but when this inhibit condition is released, the state shifts to DRDY or DIDL at line 7 or line 8. To explain this by assigning the iEND/(i-1)END conditions shown by line 7 to subunit D, when the processing of subunit D is completed, if the instruction reading is completed at the same time, the DRDY state of the next instruction is This indicates that the transition will occur. Also, like line 8, iEND・(i
-1) Explaining the END condition by assigning it to subunit D, when the processing of subunit D is completed, the next instruction reading is not in the completed state.
Indicates transition to DIDL state. In this way, each subunit undergoes a state transition.

Next, with reference to FIG. 5, it will be explained how the state transition diagram explained in FIG. 4 is used for pipeline control. The time chart in FIG. 5b shows the movement of the RDY signal of each subunit when only one instruction is executed, and it can be seen that it sequentially moves from DRDY to ERDY in four cycles.

FIG. 5a shows each subunit D31, A32,
It will be shown how the Ready signal RDY of the pipeline control unit 30 is used to sequentially move the contents of L33 and E34 from the input data line 11 to the output data line 19. The pipeline control unit 30 includes 4
Each of the subunit sections 26, 27, 28, and 29 is configured to control the state transition explained in FIG. 4, and this specific circuit will be explained later in FIG. This will be explained using Figure 7. These subunit parts 26, 27, 28,
Ready signals 47, 48, 49, 50 are output from 29 and are ANDed with the clock pulse Clock L 25 by each AND gate 43, 44, 45, 46, and connected to the clock input of each data register 35, 37, 39, 41. There is. data register 36,
38, 40, and 42 are designed to set the register output of the previous stage at Clock T. Now DRDY
When becomes "1", the data on the input data line 11 is set in the data register 35 in the D subunit. At the next Clock T, this content is transferred to register 36. The state remains like this until ARDY becomes 1. When ARDY becomes 1, the line 1
3, the contents are moved to the data register 32. At this time, if the next DRDY is set to 1 at the same time, the data of the next instruction word is set in the register 35. In this way, D→A→L→E
and the data is moved. Each subunit may process the data and then transfer it to the next stage.
It may be moved as is. Various control signals also have similar forms.

FIGS. 6 and 7 show circuits that control the state transition of subunit i. This circuit consists of subunit sections 26, 27, 28 and 29 shown in FIG. 5a.
provided for each.

In FIG. 6, flip-flops 61, 6
2 and 63 are connected to set the data D terminal input at 7Clock T, respectively iIDLT and
iRDYT, iBSYT. On the other hand, flip-flops 64, 65, and 66 are connected to set the D terminal input at Clock L, and are connected to iIDLL and iIDLL, respectively.
iRDYL, iBSYL. The last letters T and L of this symbol represent Clock T and Clock L times. The iRDY signal shown in FIGS. 5a and 5b is the output of the iRDYT flip-flop 62.

AND gate 51 is connected to (i+
1) IDLL connects B(i+1)END via line 74
is given, and the AND gate 51 sets the output line 70 to "1" on the condition that the state of the subunit (i+1) is not waiting for input (IDL) and there is a condition for inhibiting the end (END) of the subunit (i+1). Since (i+1) IDLL and B(i+1) END do not exist in this circuit corresponding to subunit E, the AND gate 51 is not provided in this circuit corresponding to subunit E. OR gate 5
2 is connected to this output line 70 and a line 69 to which a weight iEND (described later) is applied, and this OR gate 5
2 outputs BiEND on line 71. That is, when the output line 70 is "1" or the weight iEND is "1", the OR gate 52 sets BiEND, which is a condition for inhibiting the END of subunit i, to "1". This BiEND and (i-
1) IDLL is given. For this circuit corresponding to subunit D, (i-1) IDLL does not exist, and an "instruction read incomplete" signal is provided instead. AND gate 53 ENDs to own subunit i
(i-1) END is output to the output line 72 because there is no condition to suppress the subunit (i-1) and the subunit (i-1) at the previous stage is not in the input waiting state.

The signals for each state transition shown in FIG. 4b are generated by AND gates 54, 55, 56, 57, 60 and OR gates 58, 59. flip flop
The conditions for setting iIDLT61 are iIDLT=(-1).+iIDLL.(-1). =iEND, so it is the same as shown in FIG. 4b. flipflop iRDYT
The condition for setting 62 is iRDYT=(i-1)END・+iIDLL・(i-1)END. = iEND, so this is also the 4th
This is the same as shown in Figure b. flip flop
The condition for setting iBSYT63 is iBSYT=. According to the circuit of FIG. 6, subunit i
If there is no inhibiting condition BiEND, execution of the instruction can be started every cycle and completed every cycle as shown in FIG. 3a.

FIG. 7 shows a circuit for controlling the processing capacity as shown in FIGS. 3b, c, and d. iEND in Figure 6
The circuit shown in FIG. 7 is connected to the signal line 69, which is the inhibiting condition. Output line 69 in FIG. 7 is the same as signal line 69 in FIG. Output weight iEND
AND gates 80, 81, and 82 are connected to OR gate 83, and a line 84 for providing other inhibition conditions for subunit i is also connected. AND gate 80 has a signal specifying mode 1 and (i+
1) IDLL, AND gate 81 has a signal specifying mode 2, (i+1) IDLL and (i+2) IDLL
However, the AND gate 82 receives a signal specifying mode 3, (i+1) IDLL, (i+2) IDLL, and (i+
3) IDLL is given respectively. This circuit corresponding to subunit D is provided with a circuit as shown in FIG. However, for this circuit corresponding to subunit A, (i+3) IDLL does not exist, so the AND gate 82 is not provided, and for this circuit corresponding to subunit L, (i+2) IDLL does not exist.
AND (i+3)IDLL does not exist, so AND gates 81 and 82 are not provided. Further, since subunit E no longer has a subunit in the next stage, none of AND gates 80 to 82 are provided.

To illustrate the meaning of the circuit in Figure 7 with a concrete example, i=D
, if mode 1 is specified, line 69 is set to (i+1), that is, when subunit A is not IDL.
This indicates that the DEND inhibition signal weight iEND is "1". This means that when subunit D and subunit A at the next stage go into the IDL state, iEND and eventually BiEND become "0" and can transition to the RDY state. As a result, when mode 1 is specified, Figure 3b
As shown in the figure, processing is started every other cycle, resulting in half the performance of normal mode.

When mode 2 is specified, (i+1) and (i+2), that is, subunits A and L are both
This shows that the wait iEND is "1" when it is not in IDL, indicating that processing in subunit D can be started when both subunit A at the next stage and subunit L at the next stage enter the IDL state. There is. As a result, when mode 2 is specified, processing will start every two cycles as shown in Figure 3c, and when mode 2 is specified, processing will start every two cycles.
The performance is 1/3.

Furthermore, when mode 3 is designated, it means that all subunits A, L, and E become IDL, allowing subunit D to transition to the RDY state and start processing. As a result, when mode 3 is specified, processing is started every three cycles as shown in FIG. 3d, resulting in a performance that is 1/4 that of the normal mode.

The mode is designated by a panel switch, flip-flop, memory, etc., and the outputs thereof are given to signal lines 85, 87, and 89.

The present invention executes instructions while maintaining the relationship between the states of each subunit according to an operation mode that specifies the relationship between the states of each subunit, and thereby easily increases the instruction execution speed of an information processing device. can be controlled. Furthermore, by being able to set various capability values, it is possible to operate the pipeline information processing device in each mode during hardware maintenance to make it easier to detect errors.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing stages of instruction processing, Fig. 2 a and b are time charts showing the state of instruction processing, Fig. 3 a, b, c, and d are time charts showing changes in instruction processing performance; Figures 4a, b, and c are diagrams for implementing the present invention. Figure 4a is a diagram showing the definition of states taken by subunits, Figure 4b is a diagram showing state transitions, and Figure 4c is a diagram showing subunits and END. 5a is a block diagram for explaining the present invention, FIG. 5b is a time chart for explaining FIG. 5a, and FIGS. 6 and 7 are one embodiment of the present invention. FIG. 2 is a circuit diagram showing an example. 26-29...Subunit section, 30...Pipeline control section, 31-34...Subunit,
61-66...Flip-flop.

Claims (1)

[Claims] 1 In a pipeline information processing device in which the information processing device is divided into multiple subunits, each subunit sequentially shares the processing steps of one instruction word, and processes multiple instruction words at the same time, performance instructions are used. means for indicating the operating mode for each subunit, means for displaying the status of the own subunit corresponding to each subunit, and the status displayed by the displaying means of one or more subsequent subunits according to the specified operating mode. and means for controlling the transition of the display of the display means of the own subunit according to the state displayed by the display means of the subunit of the previous stage and the own stage, and the display means A pipeline information processing device characterized in that the performance is made variable by controlling the transition of the display of the subunit and controlling whether the processing of each subunit is placed in a start state or a waiting state based on the display of the display means. .