JPS5763829A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS5763829A
JPS5763829A JP13958680A JP13958680A JPS5763829A JP S5763829 A JPS5763829 A JP S5763829A JP 13958680 A JP13958680 A JP 13958680A JP 13958680 A JP13958680 A JP 13958680A JP S5763829 A JPS5763829 A JP S5763829A
Authority
JP
Japan
Prior art keywords
resist
radiation sensitive
resolving power
pattern
dry process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13958680A
Other languages
Japanese (ja)
Inventor
Hiroyuki Shigemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13958680A priority Critical patent/JPS5763829A/en
Publication of JPS5763829A publication Critical patent/JPS5763829A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To make it possible to form the pattern characterized by excellent resolving power and which is suitable even for a dry process by using two layers of negative radiation sensitive resists. CONSTITUTION:On one main flat surface of a substrate 1, a thin film 2 of the first negative radiation sensitive resist is formed, and a film 3 of the second negative radiation sensitive resist is formed thereon. Said resist films 2 and 3 have different sensitivities but have equal solubility with respect to the same solvent. The resist 2 having the higher sensitivity forms the lower layer. The radiation 4 is irradiated to the desired part of the double structured radiation sensitive resist films 2 and 3, and development is performed. Thus a convex pattern is formed. At this time, since the resolving power of the resist is determined by the thin resist 2 which forms the first layer, the pattern having the good resolving power is obtained. Since the film thickness of the central part is thick, the device is suitable even for the dry process.
JP13958680A 1980-10-06 1980-10-06 Pattern forming method Pending JPS5763829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13958680A JPS5763829A (en) 1980-10-06 1980-10-06 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13958680A JPS5763829A (en) 1980-10-06 1980-10-06 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS5763829A true JPS5763829A (en) 1982-04-17

Family

ID=15248710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13958680A Pending JPS5763829A (en) 1980-10-06 1980-10-06 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS5763829A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152199A (en) * 1991-11-27 1993-06-18 Nec Kansai Ltd Method for forming resist pattern
JP2008291524A (en) * 2007-05-25 2008-12-04 Panasonic Electric Works Co Ltd Treadboard and manufacturing method for treadboard

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152199A (en) * 1991-11-27 1993-06-18 Nec Kansai Ltd Method for forming resist pattern
JP2008291524A (en) * 2007-05-25 2008-12-04 Panasonic Electric Works Co Ltd Treadboard and manufacturing method for treadboard

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