JPS5762693A - Memory switch circuit - Google Patents

Memory switch circuit

Info

Publication number
JPS5762693A
JPS5762693A JP13853680A JP13853680A JPS5762693A JP S5762693 A JPS5762693 A JP S5762693A JP 13853680 A JP13853680 A JP 13853680A JP 13853680 A JP13853680 A JP 13853680A JP S5762693 A JPS5762693 A JP S5762693A
Authority
JP
Japan
Prior art keywords
memories
channel
memory
circuit
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13853680A
Other languages
Japanese (ja)
Inventor
Susumu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13853680A priority Critical patent/JPS5762693A/en
Publication of JPS5762693A publication Critical patent/JPS5762693A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Abstract

PURPOSE:To reduce the number of address control memories, by making the writein control of the 2nd channel memory with the address control memory and selection control memory of the 1st chanel, in a memory switch circuit for parallel two-way exchange. CONSTITUTION:The 1st channel signal applied to an input terminal 1 is given to channel memories 1100, 1110, 1101 and 1111 via a separation circuit 2 and written in through the instruction of an address counter ADR. It is read out through the information in address control memories 140, 141 and selection control memories 160, 161 through the instruction of the counter ADR, and outputted from a multiplex circuit 3 via multiplex circuit 150, 151. The 2nd channel signal applied to an input terminal 1' is applied to channel memories 1100', 1110', 1101', and 1111' via a separation circuit 2' ahd written in with the information of the memories 140, 141, 160, and 161. They are read out at the same time through the instruction of the counter ADR and outputted from a multiplex circuit 3' via selection circuits 150', 151' at selection control memories 160', 161'.
JP13853680A 1980-10-03 1980-10-03 Memory switch circuit Pending JPS5762693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13853680A JPS5762693A (en) 1980-10-03 1980-10-03 Memory switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13853680A JPS5762693A (en) 1980-10-03 1980-10-03 Memory switch circuit

Publications (1)

Publication Number Publication Date
JPS5762693A true JPS5762693A (en) 1982-04-15

Family

ID=15224441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13853680A Pending JPS5762693A (en) 1980-10-03 1980-10-03 Memory switch circuit

Country Status (1)

Country Link
JP (1) JPS5762693A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224496A (en) * 1987-03-13 1988-09-19 Kokusai Denshin Denwa Co Ltd <Kdd> Time-division channel switch circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224496A (en) * 1987-03-13 1988-09-19 Kokusai Denshin Denwa Co Ltd <Kdd> Time-division channel switch circuit
JP2509089B2 (en) * 1987-03-13 1996-06-19 国際電信電話株式会社 Time division speech path switch circuit

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