JPS5761333A - Binary and decimal system conversion device - Google Patents
Binary and decimal system conversion deviceInfo
- Publication number
- JPS5761333A JPS5761333A JP13657180A JP13657180A JPS5761333A JP S5761333 A JPS5761333 A JP S5761333A JP 13657180 A JP13657180 A JP 13657180A JP 13657180 A JP13657180 A JP 13657180A JP S5761333 A JPS5761333 A JP S5761333A
- Authority
- JP
- Japan
- Prior art keywords
- binary data
- bits
- decimal
- resistor
- binary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To perform conversion processing with high-speed when binary data are converted into decimal data, by taking out and processing the binary data by 4 bits.
CONSTITUTION: ADR (result of decimal data) resistor 106 is initialized by the output of a selector 107. While, binary data to be converted are stocked in a BR (binary data) resistor 101. Binary data stocked in the BR resistor 101 are taken out from the upper position of selection control of a selector 102 by 4 bits. The 0∼3 bits of BR resistor 101 are taken out. The binary data of these 4 bits are converted by the gate circuits 103 and 104, and becomes the input of a decimal adaptor D- ADD1 105 which performs decimal addition of 1 figure. At a result of this addition, the result of decimal addition of 4 bits and a carry signal are outputted.
COPYRIGHT: (C)1982,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13657180A JPS5761333A (en) | 1980-09-30 | 1980-09-30 | Binary and decimal system conversion device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13657180A JPS5761333A (en) | 1980-09-30 | 1980-09-30 | Binary and decimal system conversion device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5761333A true JPS5761333A (en) | 1982-04-13 |
Family
ID=15178365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13657180A Pending JPS5761333A (en) | 1980-09-30 | 1980-09-30 | Binary and decimal system conversion device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5761333A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59177645A (en) * | 1983-03-29 | 1984-10-08 | Nec Corp | Binary-decimal converting system |
JPS60150135A (en) * | 1983-09-30 | 1985-08-07 | ハネイウエル・インフオ−メ−シヨン・システムス・インコ−ポレ−テツド | Method and apparatus for converting binary format number to decimal format number |
US8892615B2 (en) | 2011-03-29 | 2014-11-18 | Fujitsu Limited | Arithmetic operation circuit and method of converting binary number |
-
1980
- 1980-09-30 JP JP13657180A patent/JPS5761333A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59177645A (en) * | 1983-03-29 | 1984-10-08 | Nec Corp | Binary-decimal converting system |
JPS60150135A (en) * | 1983-09-30 | 1985-08-07 | ハネイウエル・インフオ−メ−シヨン・システムス・インコ−ポレ−テツド | Method and apparatus for converting binary format number to decimal format number |
US8892615B2 (en) | 2011-03-29 | 2014-11-18 | Fujitsu Limited | Arithmetic operation circuit and method of converting binary number |
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