JPS6414636A - Data multi-division type arithmetic unit - Google Patents

Data multi-division type arithmetic unit

Info

Publication number
JPS6414636A
JPS6414636A JP62168722A JP16872287A JPS6414636A JP S6414636 A JPS6414636 A JP S6414636A JP 62168722 A JP62168722 A JP 62168722A JP 16872287 A JP16872287 A JP 16872287A JP S6414636 A JPS6414636 A JP S6414636A
Authority
JP
Japan
Prior art keywords
data
carry
calculation
processing
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62168722A
Other languages
Japanese (ja)
Inventor
Shigeru Matsuo
Akihiro Katsura
Masahiko Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Engineering Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP62168722A priority Critical patent/JPS6414636A/en
Publication of JPS6414636A publication Critical patent/JPS6414636A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need of the calculation pre-processing and the calculation post-processing for a partial calculation, and to simplify the control, by providing a means for switching lower carry and upper carry positions to arbitrary length, on a carry look-ahead circuit. CONSTITUTION:A lower carry input signal of a carry look-ahead circuit is connected to the lowest bit of a partial data position and switched to a carry signal from the lower one of all the data. Also, an upper carry output signal is outputted from the uppermost bit of the partial data position, and switched to a carry signal to the upper one of all the data. For instance, when the data is constituted of a 32 bit data and divided into two, and two data of 16 bits are handled, the data of 16 bits extending from the data A0 to A15 of an arithmetic circuit 10, and the data of 16 bits extending from B0 to B15 are inputted, and in case of executing the calculation, the lower carry input is executed to '0' bit of a CLA (carry look-ahead), and an upper carry of 15 bits is outputted. In such a way, the pre-processing and the post-processing of the partial data calculation are not required.
JP62168722A 1987-07-08 1987-07-08 Data multi-division type arithmetic unit Pending JPS6414636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168722A JPS6414636A (en) 1987-07-08 1987-07-08 Data multi-division type arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168722A JPS6414636A (en) 1987-07-08 1987-07-08 Data multi-division type arithmetic unit

Publications (1)

Publication Number Publication Date
JPS6414636A true JPS6414636A (en) 1989-01-18

Family

ID=15873221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168722A Pending JPS6414636A (en) 1987-07-08 1987-07-08 Data multi-division type arithmetic unit

Country Status (1)

Country Link
JP (1) JPS6414636A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008532854A (en) * 2004-11-23 2008-08-21 ビル ロウ， Knob feeder for beverage containers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008532854A (en) * 2004-11-23 2008-08-21 ビル ロウ， Knob feeder for beverage containers

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