JPS59177645A - Binary-decimal converting system - Google Patents

Abstract

PURPOSE:To reduce the number of times of operation by decomposing binary data into blocks, each of which consists of a preliminarily determined number of bits, in order from the least significant bit and storing these blocks and converting blocks to decimal data in order from the low-order block and shifting up data in accordance with positions occupied by blocks to add data successively. CONSTITUTION:First, counters 10 and 15 are cleared to 0, and binary data in a register 14 is transferred to a shifter 18 through a selecting circuit 16 and an adding circuit 17, and, for example, the lowest 4 bits of data are sent to a latch circuit 12. A corresponding address of a converting circuit 13 is accessed in accordance with contents of the latch circuit 12 and the counter 10 to convert this 4-bit data to decimal data, and this decimal data is added to contents of the register 15 by the adding circuit 17, and the result is shifted by the shifter 18 and is stored in the register 15, and the counter 10 is counted up. Next, binary data from the register 14 is transferred to the shifter 18, and the next lowest 4 bit are subjected to the similar processing. This operation is repeated to convert binary data in the register 14 to decimal data, and decimal data is stored in the register 15. Thus, the number of times of converting operation is reduced to 1/4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention converts binary form data (hereinafter referred to as binary data) into binary code 10 by using a microprogram controlled data processing device.
Convert to decimal format data (hereinafter referred to as decimal data) 2
Regarding the base-decimal conversion method.

Conventional binary-to-decimal conversion is performed by examining each bit of binary data. That is, first, the content of the most significant bit of the binary data is doubled and stored in a suitable storage means such as a register, and then the content of the storage means next to the most significant bit is doubled. can get.

However, in such a conventional conversion method, if the binary data is n (positive integer) bits, an arithmetic unit is required to perform n multiplication and addition operations.

Therefore, the number of steps in the microprogram for controlling the conversion operation increases, resulting in a decrease in calculation speed and processing time.

The second object of the present invention is to provide a binary-to-decimal conversion method that eliminates the above-mentioned drawbacks.

The system of the present invention is a binary-to-decimal conversion method for converting binary format data into binary coded decimal format data. 1 storage means, selection means for selecting one of a plurality of bit parts within the binary data, and a bit part indicating which part of the binary data the selected bit part is. a position display means, a conversion means for converting the selected bit portion into binary coded decimal format data based on the indication of the display means, and an addition means for adding decimal data, Each bit portion is converted into decimal form data and the conversion results are added to perform conversion into binary form data.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. here,
- As an example, a case will be explained in which 16-bit binary data is converted to decimal data.

Since the binary data is 16 bits, converting it to a decimal number results in a maximum of 5 digits. In 1o base data,
Since one decimal digit is represented by 4 bits, 4 (bits) x 5 (digits) = 20 bits are required. here,
Each internal bus has a 20-bit configuration so that 20-bit processing can be performed.

The output of the conversion circuit 13 is applied to one input of the decimal adder 17 via the selection circuit 16. Register files 14 and 15 having a plurality of 20-bit registers are controlled by a microprogram for addressing, reading and writing of the registers. shifter 1
8 performs bit shift in units of 4 bits in this embodiment. A counter 10 and a counter control circuit 11 that controls the counter 10 are controlled by a microprogram, and the lower two bits of the counter 10 are input to a conversion circuit 13. The register file 14 stores in advance 16-bit binary data to be converted.

Conversion circuit 13rl: Consists of a memory only for entertainment (ROM), and an outline of its contents is shown in FIG.

In FIG. 2, the ■ column shows the 2-bit input from the counter 10 (C column) and the 4-bit input from the latch circuit 12 (Pa
: indicates an address expressed in hexadecimal notation). Further, column O shows the contents of each address of the ROM.

For convenience of explanation, the 0 column is divided into 5 parts every 4 bits and the contents of C are expressed in decimal notation. The contents of each address in the ROM are determined as follows. Here, the contents of column P vi
(expressed in decimal notation), and the content of the D grab is Di (expressed in decimal notation).

■If the contents of the column are (oooooo) to (001111): Di=i ■If the contents of the column are (010000) to (011111): Di=iX16 If the contents of the ■ column are (1ooooo) to (101111) :Di=iX162 When the contents of the ■ column are (110000) to (111111): Di=iX163 Transfer the binary data C stored in the tough aisle 14 to the shifter 18 via the selection circuit 16 and the decimal addition circuit 17. . Next, four bits starting from the least significant bit in the seven-folder 18 are transferred to the latch circuit 12. Furthermore, (2) the contents eQ of the register in the register file 15 for storing the partial sum are set. Next, (3) depending on the contents of the latch circuit 12 and counter 10! The corresponding address in the llll conversion circuit 13 is accessed, the contents thereof and the contents of the register file 15 are added in decimal form by the adder 17, and the addition result is stored in the register file 15 via the 7-cap 18, and the counter 10 count up.

Next, (4) the same binary data is transferred from the register file 14 to the shifter 18, (5) it is shifted 4 bits in the direction of the least significant bit in the shifter 18, and (6) the 4 bits are shifted from the least significant bit. The data is transferred to the latch circuit 12. Furthermore, (7) access the corresponding address in the conversion circuit 13 according to the contents of the latte circuit 12 and the counter IO,
Adder 17 adds the contents and the contents of register file 15.
Then, the result is stored in the C register file 15 via the shifter 18, and the counter amplifies the decimal count. (7) After performing the operation in (4) above, move 8 to the least significant bit in thick 18.
The bit shifter performs the operations (6) and (7) above. Furthermore, (8) after performing the operation in (4) above, the shifter 18 shifts 12 bits in the direction of the least significant bit, and performs the operations in (6) and (7) above.

After completing the above operations, 2 files will be created in the register file 15.
A value obtained by converting decimal data into decimal data is obtained.

In this embodiment, the binary data is transferred from the register file 14 to the chic 18 every time the decimal addition q- is iterated, but another chic is provided separately from the shifter 18.
It may be configured such that the transfer of binary data for each decimal addition can be omitted.

As described above, in the present invention, by dividing n-bit binary tech into fm bits low-order and converting this into decimal data,
Is it possible to improve the calculation speed by performing the n-time calculations that were previously required? : It has the effect of being achievable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a table showing the contents of the conversion circuit 13. In the figure, 10...counter, 11...
...Counter control, 12...Latch circuit, 13...19. Conversion circuit, 1.4.15...
...Register file, 16...Selection circuit, 1
7... Decimal adder, 18°°°° shifter. Procedural amendment (formality) 1. Display of incident 1982 Patent Application No. 5294
No. 7 No. 2, Title of the invention Binary-decimal conversion method 3, Relationship with the case of the person making the amendment Applicant No. 33-1 (423) Shibago J-1”l, Minato-ku, Tokyo Representative of NEC Corporation Tadahiro Sekimoto 4, Agent Address: 137-8 Shiba 5-chome I-Ko, Minato-ku, Tokyo 108 Sumitomo 3F Building 1, Hondenki Co., Ltd. (6591) Patent Attorney Susumu Uchihara Telephone: Tokyo (03) 456-31. 1.1 (Main representative) ゛・(Contact information: 11 Hondenki Co., Ltd. i1・Kaitobu) 6. Column L of “Brief explanation of drawings” in the specification subject to amendment Contents of amendment 1 Brief explanation of drawings” In column 8, page 8, line 6, the statement ``It is a table'' is corrected to ``It is a diagram.''

Claims (1)

[Claims] In a binary-decimal conversion method for converting binary format data into binary coded decimal format data, a storage means for storing binary format data having a plurality of bit parts each having a predetermined number of bits; a selection means for selecting one of a plurality of bit parts in the form data; a bit part position display means for indicating which part in the binary form data the selected bit part is; It is equipped with a conversion means for converting the bit part into binary coded 1 (decimal form data) based on the display of the display means, and an addition means for performing decimal addition, and converts each bit part into binary coded decimal form data. A binary-decimal conversion method whose % characteristic is to convert binary form data to binary 1O-adic form data by performing the conversion and adding each variable resultant red.