JPS6155690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decimal arithmetic device in a data processing device.

Traditionally, decimal operations, especially decimal multiplication and division and decimal 2
In decimal conversion and binary/decimal conversion, in order to create multiples of a decimal number, the number is passed through an arithmetic unit that can perform decimal addition and subtraction several times, or the result that is passed through a limited multiple generation circuit is used as input to the arithmetic unit. there was. Therefore, it has the disadvantage that many processing steps are required until the desired calculation result is obtained.

An object of the present invention is to provide a decimal arithmetic device that operates at high speed.

In order to achieve the above object, a decimal arithmetic device according to the present invention converts a binary coded decimal number from 8421 code to 5421 code.
A circuit in which multiple stages of binary coded decimal doubling circuits are connected in cascade, which doubles the binary coded decimal number by shifting it one bit to the left after converting it to a code, or a binary coded decimal number doubling circuit.
After shifting the decimal number to the right, the 5421 code becomes 8421
1/2 binary coded decimal number by converting it to code
Any of the circuits in which multiple stages of binary coded decimal number 1/2 times circuits are connected in cascade, or the binary coded decimal number 2 that doubles the number
A circuit equipped with both multi-stage cascade circuits of a doubler circuit and a binary coded decimal 1/2 doubler circuit, and
A multiple selection circuit that takes as input the 2 ^±n times the output of each stage of the decimal number doubler circuit or the binary coded decimal number 1/2 times circuit, and selects and outputs either of the above 2 ^±n times the output based on the multiple specification information. It is composed of.

According to the above structure, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows an embodiment of a circuit that is the basis of the present invention. Figure 1 a is from 8421 code for 1 decimal digit
Code converted to 5421 code and shifted 1 bit to the left.
Figure 1b shows a decimal 1/2 circuit that has been shifted one bit to the right and converted the code from 5421 code to 8421 code. Figure 1c shows the 8421 code and 5421 code. The conversion table and the formula below are its logical formulas.

b ₀ = a ₀ + a ₁ a ₂ + a ₁ a ₃ b ₁ = a ₀ a ₃ + a _{1 2 3} b ₂ = a ₂ a ₃ + a _{0 3} + ₁ a ₂ b ₃ = _{0 1} a ₃ + a ₁ a _{2 3} +a _{0 3} a ₀ =b ₀ b ₁ +b ₀ b ₂ b ₃ a ₁ = ₀ b ₁ +b _{0 1 2} +b ₀ b _{2 3} a ₂ = ₀ b ₂ +b _{0 2} b ₃ +b _{2 3} a ₃ = b _{0 3} + ₀ b ₃ Since the decimal numbers to be input are from 0 to 9, 5421 codes for 8421 codes of 10 or more are not used. Therefore, the logical formula holds true for decimal numbers 0 to 9. As shown in FIG. 1c, a binary coded decimal number input in 8421 code passes through a conversion circuit constructed using the above-mentioned logical formula and is converted into 5421 code.

The 8421 code and 5421 code have the following characteristics.

First, the most significant bit _b0 of the 5421 code can be correctly carried to a higher digit when the input binary coded decimal number (8421 code) is doubled.

When the lower bits b ₁ , b ₂ , b ₃ of the second 5421 code are shifted to the left by 1 bit, the input binary code is
A value that is twice the decimal number (8421 code) can be generated.

Thirdly, when shifting 1 bit to the left, the lower 1 bit shift of _b3 of the 5421 code becomes blank due to the shift.

Normally, a carry from the lower digit is inserted at this position. If there is no lower digit, it may be fixed to 0.

Fourth, since the carry to the upper digit and the carry from the lower digit are at most 1, a 1-bit left shift is sufficient. From the above characteristics, by connecting multiple stages of this doubling circuit, the output at each stage will appear as 2 ⁿ times the binary coded decimal number input at the beginning.

The above description was about the double circuit, but the same applies to the 1/2 circuit, and it can be considered that the configuration of the double circuit is completely reversed.

FIG. 2 shows an embodiment of a circuit that generates multiples based on the doubling circuit 1 and the 1/2 multiplying circuit 2. Stacked in 4 layers each, ×1, ×2, ×4, ×8, ×16, ×
The multiples generating 1/2, ×1/4, ×1/8, and ×1/16 are selected and output by the multiple selection circuit 3 according to external specifications. Each stage has a terminal for inputting from the outside and a terminal for outputting to the outside by a 1-bit shift, and these are connected to adjacent digits when processing multiple decimal digits. FIG. 3 shows a connected configuration for a three-digit decimal number.

Next, the operation will be explained step by step based on FIG.
When a 1-digit decimal number that generates a multiple is input, it is converted from an 8421 code to a 5421 code in the doubling circuit 1, and by shifting the code 1 bit to the left, the decimal number is doubled. Furthermore, the second stage output is 4 times, and the third stage output is 8 times
It is multiplied by 16 at the 4th stage output.

On the other hand, add 1 digit of the decimal number for which you want to generate the above multiple.
After shifting the bits to the right, 1/2 circuit 2 converts the code from 5421 code to 8421 code.
The value multiplied by 1/2 in decimal is output. 1/4 times the 2nd stage output, 1/8 times the 3rd stage output, 1/4 times the 4th stage output
A value multiplied by 16 is generated. The values generated by each multiple are collected in the multiple selection circuit 3, and the desired multiple is generated according to an external multiple instruction.
This is a multiple generation circuit for a three-digit decimal number when three of the circuits shown in FIG. 2 are connected in the digit direction. An even larger multi-digit multiple generation circuit can be constructed by expanding in the digit direction.

In this embodiment, the multiples are 16 times and 1/16 times, but many multiples can be generated by stacking decimal 2x circuits and decimal 1/2x circuits.

As explained in detail above, according to the present invention, 10
Decimal calculation speed can be increased by stacking multiple decimal double circuits and 1/2 double circuits to generate multiples of decimal numbers, generate multiples, and select based on external instructions.

[Brief explanation of the drawing]

Figure 1a is a circuit diagram of a decimal doubler circuit, and Figure 1b is a circuit diagram of a decimal doubler circuit.
Schematic diagram of hex 1/2 circuit, figure c is from 8421 code
Figure 2 is a circuit diagram showing an embodiment of the decimal arithmetic device according to the present invention.
This is an example of generating multiples for a single digit of a base number. FIG. 3 is a circuit diagram showing another embodiment of the present invention, in which multiples are generated for a three-digit decimal number. 1...Decimal double circuit, 2...Decimal 1/2 times circuit,
3...Multiple selection circuit.

Claims (1)

[Claims] 1 A circuit in which multiple stages of binary coded decimal number doubling circuits are connected in cascade, or a binary coded decimal number doubling circuit that doubles the binary coded decimal number by converting the binary coded decimal number from 8421 code to 5421 code and then shifting it one bit to the left. Either one of the circuits in which multiple stages of binary coded decimal 1/2 times circuits are connected in cascade, which doubles the binary coded decimal number by 1/2 by shifting the decimal number to the right and converting it from 5421 code to 8421 code. A circuit comprising both multi-stage cascade circuits of the binary coded decimal number double circuit and the binary coded decimal number 1/2 time circuit, and the binary coded decimal number double circuit or the binary coded decimal number 1/2 time circuit. 1. A decimal arithmetic device comprising: a multiple selection circuit which receives the 2 ^±n times the output of each stage as input and selects and outputs one of the 2 ^{±n times} the output based on multiple designation information.