JP2002222078A - Binary-decimal conversion circuit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a binary-decimal conversion circuit which is increased in the processing speed for conversion from a 4-bit binary number to a decimal number. SOLUTION: This circuit has a decimal adder 13 which adds decimal data and has two data inputs and a carry input, a decimal-binary 20-multiple generating circuit 15, and a decimal 4-multiple generating circuit 16, and inputs the output of the decimal 20-multiple generating circuit 15 inputting the output of a decimal data register 14 as an arithmetic result to the high-order part of one input of the decimal adder 13 and the most significant 4 bits of the binary data register 12 holding binary data to be converted to the low-order part of a decimal 20-multiple inputted to one input of the decimal adder 13. Further, data generated by inverting the output of the decimal 4-multiple generating circuit 16 inputting the arithmetic result are inputted to the other input of the decimal adder and 1 is always inputted to the carry input of the decimal adder 13 to generate a complement of 2 to the decimal 4-multiple.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting a binary number into a decimal number in an information processing apparatus, and in particular, to a binary number which converts a binary number into a decimal number by 4 bits to increase the conversion speed. The present invention relates to a decimal conversion circuit.

[0002]

2. Description of the Related Art In a conventional binary-decimal conversion circuit,
For example, conversion is performed by checking each bit of binary data bit by bit as in the technique described in Japanese Patent Application Laid-Open No. Sho 59-168543.

FIG. 9 is a block diagram showing this conventional technique. Referring to FIG. 9, this binary-decimal conversion circuit includes a binary data selector 11 and a binary data register 1.
2, decimal adder 13 and decimal data register 14
It is composed of

The binary data 000 to be converted and the data 300 obtained by shifting the binary data register 12 to the left by one bit are input to the binary data selector 11, and the output 100 of the binary data selector 11 is input to the binary data register 12. type in,
The output 500 of the decimal data register 14 is input to both inputs of the decimal adder 13, the most significant bit 200 of the binary data register 12 is input to the carry input of the decimal adder 13, and the decimal adder 13 is input to the decimal data register 14.

[0005] First, binary data 000 to be converted is transferred to a binary data register 12 via a binary data selector 11.
And reset the decimal data register 14 at the same time.

Next, the most significant bit 200 of the binary data register 12 and the data 500 of the decimal data register 14
Are added by the decimal adder 13 to add the double number of the value 500 of the decimal data register 14 and the most significant bit 200 of the binary data register 12. Also,
The output 400 of the decimal adder 13 is stored in the decimal data register 14, and at the same time, the data 300 obtained by shifting the data of the binary data register 12 to the left by one bit is transferred via the binary data selector 11 to the binary data register 12. To be stored.

This operation is repeated by the number of bits of binary data, thereby performing binary-decimal conversion.

[0008]

SUMMARY OF THE INVENTION The above-described conventional binary 1
In the zero-ary conversion circuit, assuming that the binary data has n (positive integer) bits, the arithmetic circuit is required to perform an addition operation n times. For this reason, there is a disadvantage that the execution time required for the binary-decimal conversion is increased, which causes a reduction in the operation speed and an increase in the processing time. For this reason, Japanese Patent Application Laid-Open No. 2000-2001
No. 74 has made an improvement to perform binary-to-decimal conversion for each three bits in one operation cycle. In the present invention, however, further processing is performed for each four bits, thereby further increasing the speed.

[0009]

SUMMARY OF THE INVENTION A first binary 10 according to the present invention.
The decimal conversion circuit includes a decimal 20-fold generation circuit for multiplying decimal data by 20, a decimal 4-fold generation circuit for quadrupling decimal data, and a binary value to be converted. When a 4-bit binary value is output, a binary data register that shifts the binary value to the left by 4 bits in preparation for the next operation cycle, and inputs the upper 4 bits at the left end of the binary data register to input 5 bits of 10 bits A 4-bit binary-decimal converter for converting to a decimal value, the output data of the 20-fold decimal generation circuit and the output data of the 4-bit binary-decimal converter as a first data input,
A decimal adder that uses the data obtained by inverting the output data of the multiple generation circuit as a second data input and inputs a carry of 1 to add the first data input and the second data input;
A decimal data register for holding the operation result of the decimal adder and outputting the data held in the decimal 20-times multiple generation circuit and the decimal 4-times generation circuit in the next operation cycle; Output of a 4-bit binary value from the decimal data register and 1 from the decimal data register
It is characterized in that the output of the 0-base value is performed synchronously in one operation cycle.

According to a second binary-decimal conversion circuit of the present invention, in the first invention, the 20-fold decimal data output from the 20-fold decimal number generating circuit and the lower 5 bits of the 20-fold decimal data are 4 bits 2
The output data of the decimal-decimal converter is taken into the position of the lower 5 bits and used as a first data input, and the data obtained by inverting the decimal quadruple by the decimal quadruple generation circuit is used as a second data input. There is provided a decimal adder for adding the 20-fold decimal data, the output data of the 4-bit binary-decimal converter, and the 4-fold decimal data in one operation.

[0011] The third binary-decimal conversion circuit according to the first or second invention, wherein the operation result in the previous operation cycle is based on the first data input and the second data input. And a decimal adder for outputting a numerical value that sums the output result of the 4-bit binary-decimal converter to a 16-times decimal number.

The fourth binary-decimal conversion circuit of the present invention is the first invention, wherein the first binary-decimal number generating circuit for doubling the decimal data is connected in series in two stages.
A quadruple-number generation circuit is provided.

The fifth binary-decimal conversion circuit according to the first invention is the same as the first invention, except that the double-decimal number is generated by the double-decimal number generating circuit and the result is shifted to the left by 4 bits. And a decimal 20-fold multiple generation circuit for generating a binary 20-fold multiple.

A sixth binary-decimal conversion circuit according to the first invention is the decimal data register for storing the converted decimal value of the binary value stored in the binary data register. Is provided.

According to the first binary-decimal conversion method of the present invention, when the upper 4 bits of a binary value to be converted are output, the binary value is shifted by 4 bits to the left, and the next arithmetic cycle is executed. A first step of preparing, a second step of converting the 4-bit binary value output in the first step into a 5-bit decimal value, and a 20-bit decimal number generated in the previous operation cycle A third step of generating a multiple and a quadruple, a fourth step of inverting the quadruple generated in the third step, and 1 of a second step.
A decimal number is generated by inputting a 0-ary value and a 20-fold multiple of the third step as a first input, a quadruple inverted in the fourth step as a second input, and inputting 1 into a carry to perform addition, thereby generating a decimal number. And a sixth step of holding the result generated in the fifth step and outputting the result to the third step in the next operation cycle.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention.

Referring to FIG. 1, binary data 000 to be converted, which is binary data and is converted to a decimal number.
And a binary data selector 11 for selecting and taking in data 300 obtained by shifting the output data of the binary data register 12 to the left by 4 bits. The output 100 of the binary data selector 11 is input to the binary data register 12.

The upper 4 bits of the binary data register 12 are sequentially taken in by a 4-bit binary-decimal converter 18 corresponding to the operation cycle, and the 4-bit binary number is converted into a 5-bit decimal number. It is supplied to a decimal adder 13.

The output 9 of the decimal data register 14
00 is input to a decimal 20-fold generation circuit 15 that generates a decimal value to be multiplied by 20, and a decimal quadruple generation circuit 16 that also generates a decimal value to quadruple the output 900.

Then, the output 400 of the decimal 20-multiple generating circuit 15 (the least significant 5 bits are 00000 for the 20-multiple) is input to one input position of the two inputs of the decimal adder 13. The 5-bit decimal value output from the 4-bit binary-decimal converter 18 is converted to a decimal 20
The data 400 obtained by inverting the output 500 of the decimal quadruple number generating circuit 16 by the inverting circuit 17 is taken as it is into the decimal adder 13
, And 1 is always input to the carry input 700 of the decimal adder 13 to execute the addition operation of the decimal value by the decimal adder 13. Decimal adder 13
Is stored in the decimal data register 14.

Referring to FIG. 2, a decimal double number generating circuit for generating a decimal value twice as large as an input numerical value includes j-digit (j is a positive integer) decimal data d0 (0), d0 ( 1), d0 (2), d0 (3),.
.., di-1 (0), di-1 (1), di-1
(2), di-1 (3), di (0), di (1), d
i (2), di (3), di + 1 (0), di + 1
(1), di + 1 (2), di + 1 (3),..., D
j-1 (0), dj-1 (1), dj-1 (2), dj
From -1 (3), decimal double data D-1 (3), D0 (0), D0 (1), D0 (2),
..., Di-2 (3), Di-1 (0), Di-1
(1), Di-1 (2), Di-1 (3), Di
(0), Di (1), Di (2), Di (3), Di +
1 (0), Di + 1 (1), Di + 1 (2),...
Dj-2 (3), Dj-1 (0), Dj-1 (1), D
j-1 (2) so as to generate 1-digit decimal double generation circuits 20 to
24 (they all have the same configuration).

FIG. 3 is a detailed circuit diagram of the single-digit decimal double generation circuits 20 to 24 of FIG.

FIG. 4 shows a single-digit decimal double generation circuit 20.
24 is a conversion table of FIG.

As shown in FIG. 4, one digit consisting of four bits of decimal data is from "0" to "9" of the decimal number, and its double is from "0" to "18". Yes, the least significant bit D of the conversion digit of the result of generating a decimal double number
(3) is always "0". FIG. 5 is a conversion table in units of one digit of the circuit for generating a decimal double number of a plurality of decimal numbers. In the generation of a decimal double of a multi-digit decimal number, one bit carries from the lower digit, but as described with reference to FIG. 4, the least significant bit of each digit is doubled to “0”. Therefore, one bit of carry from the lower digit can be directly input.

Therefore, any one digit of di (0), di (1), di of a j-digit (j is a positive integer) decimal number
(2), di (3) is a decimal double Di-1 (3), D
When converting to i (0), Di (1), Di (2), Di (3) (i is a positive integer from 0 to j-1), Di-1 (3) = di (0) + di (1) ) * (Di
(2) + di (3)) Di (0) = di (0) * di (3) + di (1)
* Di (2) '* di (3)' Di (1) = di (0) * di (3) '+ di
(1) '* di (2) + di (2) * di (3) Di (2) = di (0)' * di (1) '* di
(3) + di (1) * di (2) * di (3) '+ di
It can be generated by the logic of (0) * di (3) ′. (Where "*" is a logical product,
“+” Indicates a logical sum, and “′” indicates an inversion (complement). Therefore, the decimal 1-digit double doubling circuit of FIG.
As shown in FIG. 2, by connecting them in parallel to form a decimal double number generation circuit, it is possible to generate a decimal double number of a decimal number of a plurality of digits. This double number generation circuit is connected in series to 2
The combination of stages realizes the decimal quadruple number generation circuit 16.

Referring to FIG. 7, the decimal 20 multiple generation circuit 15 generates j-digit (j is a positive integer) decimal data d0 (0), d0 (1), d0 (2), d0 (3).・
-Di-1 (0), di-1 (1), di-1 (2), d
i-1 (3), di (0), di (1), di (2),
di (3), di + 1 (0), di + 1 (1), di +
1 (2), di + 1 (3), ..., dj-1 (0),
From dj-1 (1), dj-1 (2), dj-1 (3), decimal multiple data E0 (0), E0 (1), E0 (2), E0 (3), etc.
Ei-1 (0), Ei-1 (1), Ei-1 (2), E
i-1 (3), Ei (0), Ei (1), Ei (2),
Ei (3), Ei + 1 (0), Ei + 1 (1), Ei +
1 (2), Ei + 1 (3), ..., Ej-1 (0),
Ej-1 (1), Ej-1 (2), Ej-1 (3), E
j (0), Ej (1), Ej (2), and Ej (3) are generated.

The 20-fold decimal data can be obtained by using the above-mentioned double-decimal number generating circuit and multiplying the output by 10 times. Output decimal data 90 of decimal data register 14
0 is input to the decimal double number generation circuit to generate a decimal double number, and the output is shifted to the left by one digit (4 bits) (as a characteristic of the decimal number, 10 times the decimal number is 4 bits at the least significant digit)
Can be obtained simply by adding 0 to ) To generate a decimal 20 multiple of a decimal number.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

The operation of the embodiment of the present invention will be described with reference to FIGS.

FIG. 6 shows an example of binary data such as "0".
0001110010000110110 "is a state transition table showing the operation of converting each constituent circuit in each operation cycle in the case of converting" 0001110010000110110 "to decimal data. (If this binary value is converted to a decimal number, it is a five-digit 58422. First, the binary data 000 to be converted is loaded into the binary data register 12 via the binary data selector 11, and the first four bits of the binary data register are taken out.
It is input to a bit binary-decimal converter 18 and converted to a 5-bit decimal number. FIG. 8 shows the contents of the conversion.

At the same time, the decimal data register 14 is reset to 0.

Next, the decimal data 900 in the decimal data register 14 is used to generate 1
It generates 20-fold decimal 0 data 400 (data excluding the least significant 5 bits). Further, a decimal quadruple number generating circuit 16 generates a decimal quadruple number 500, and an inverting circuit 17 generates inverted data 600.

The 5-bit data converted by the 4-bit binary-decimal converter 18 as shown in FIG.
The decimal adder 13 adds the inverted data 600, which is inserted into the lower 5 bits of the output 400 of the 0 multiple generation circuit 15 and inverted from the data output from the output 500 of the decimal quadruple generation circuit 15, by the decimal adder 13. At this time, "1" is always input to the carry input 700 of the decimal adder 13. Thus, the addition of three decimal values is performed in one operation.

As a result, the decimal value converted by the 4-bit binary-decimal converter is added to the numerical value output from the decimal 20-multiple generating circuit, and the numerical value output from the decimal quadruple-generating circuit 16 is obtained from this numerical value. Is to be subtracted.
As a result, the most significant 4 bits of the binary data register 12 have been added to the 16 times (20 times to 4 times) value of the decimal data register 14.

The output 800 of the decimal adder 13 is 1
At the same time as storing the data 300 in the binary data register 12, the data 300 obtained by shifting the data in the binary data register 12 to the left by 4 bits is stored in the binary data register 12.

According to FIG. 6, in the first operation cycle, the decimal data register 14 is initialized.
00000 "(decimal) is taken out and input to the decimal 20-times multiple generation circuit 5 and the decimal 4-times multiple generation circuit 16 to generate the decimal 20-times multiple and the quadruple-times multiple, respectively. (0000) and the first four bits (0000) of the binary data register 12 are converted to decimal numbers (00), and the decimal quadruples are inverted to 2's complement (0000) to carry 1's. Source 10
The decimal adder 13 subtracts a quadruple decimal from a 20-fold decimal. As a result of this addition, a decimal number (00000) is obtained in the first operation cycle.

In the second operation cycle, the outputs from the decimal 20 multiple generation circuit 15 and the decimal quadruple generation circuit 16 output the same decimal number (00000) as in the first arithmetic cycle.
However, since the contents of the binary data register 12 are shifted to the left by 4 bits, a binary number (1110) is output. Therefore, the conversion result of the 4-bit binary-decimal converter 18 is a decimal number (14). Is output. Thereby, 10
Decimal number (14) is 10
Output to the binary data register 14.

In the third operation cycle, the decimal (14), which is the content of the decimal data register 14, is extracted, and the decimal 20 multiple generation circuit 15 outputs the decimal (14).
Hexadecimal (280 = 14X20) is the decimal quadruple generation circuit 1
6 produces a decimal (56 = 14 × 4). 2
From the binary data register 12, a binary number (0100) shifted further to the left by 4 bits is extracted, and a 4-bit binary 10
It is converted to a decimal number (04) by the decimal converter 18.
The above values are calculated by the decimal adder 13 (28
0 + 4-56) As a result, 228 is output to the decimal data register 14.

The above processing is repeated, and as a result, 58422 as shown in FIG. 6 can be obtained in the decimal data register 14.

By repeating this operation by a quarter of the number of bits of the binary data, the binary data 000 to be converted is converted into the decimal / decimal data 900. In this way, according to the present invention, the binary data “000001110010000111010” is converted to 10
Is converted to binary data “58422”.
This can be realized with 1/4 cycle number of the bit number of binary data.

[0042]

According to the present invention, n-bit binary data is converted to 4 bits.
By converting the data into decimal data in bit units, the number of operations of n times per bit conventionally required becomes n / 4 times,
There is an effect that the calculation speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a circuit that generates a decimal double according to the present invention.

FIG. 3 is a circuit diagram for generating a single-digit decimal double according to the present invention;

FIG. 4 is a conversion table at the time of generating a one-digit decimal double according to the present invention.

FIG. 5 is a conversion table at the time of generating a decimal double at the time of multi-digit conversion according to the present invention.

FIG. 6 is a state transition table using an embodiment when converting a binary number to a decimal number according to the present invention.

FIG. 7 is a block diagram illustrating a configuration of a circuit that generates a decimal 20 multiple according to the present invention.

FIG. 8 is a conversion table showing conversion results of the 4-bit binary-decimal converter of the present invention.

FIG. 9 is a block diagram showing a conventional binary-decimal conversion circuit.

[Explanation of symbols]

 000 Conversion target binary data 11 Binary data selector 12 Binary data register 13 Decimal adder 14 Decimal data register 15 Decimal 20 multiple generation circuit 16 Decimal quadruple generation circuit 17 Inverting circuit 18 4-bit binary decimal Converter 400 Decimal 20 times 500 Decimal 4 times 700 Carry input 900 Decimal data

Claims (7)

[Claims] 1. A decimal 20-fold generation circuit for multiplying decimal data by 20, a decimal 4-fold generation circuit for quadrupling decimal data, and a binary value to be converted are stored and stored in accordance with an operation cycle. When a 4-bit binary value is output, a binary data register that shifts the binary value to the left by 4 bits in preparation for the next operation cycle, and inputs the upper 4 bits at the left end of the binary data register to input 5 bits of 10 bits A 4-bit binary-decimal converter for converting to a decimal value, the output data of the 20-fold decimal generation circuit and the output data of the 4-bit binary-decimal converter as a first data input,
A decimal adder that uses the data obtained by inverting the output data of the multiple generation circuit as a second data input and inputs a carry of 1 to add the first data input and the second data input;
A decimal data register for holding the operation result of the decimal adder and outputting the data held in the decimal 20-times generation circuit and the decimal 4-times generation circuit in the next operation cycle; A binary-to-decimal conversion circuit for synchronizing the output of a 4-bit binary value from a decimal data register and the output of a decimal value from the decimal data register in one operation cycle. 2. The four-bit binary one using the fact that the decimal twenty-multiple data output from the decimal twenty-multiple generation circuit and the lower five bits of the decimal twenty-multiple data are 0.
The output data of the zero-decimal converter is taken into the position of the lower 5 bits and used as the first data input, and the data obtained by inverting the decimal quadruple by the decimal quadruple generation circuit is used as the second data input. 2. The decimal adder according to claim 1, further comprising a decimal adder that adds the 20-fold decimal data, the output data of the 4-bit binary-decimal converter, and the 4-fold decimal data in one operation. Decimal-decimal conversion circuit. 3. A decimal 1 of an operation result in a previous operation cycle based on the first data input and the second data input.
3. The binary-decimal conversion circuit according to claim 1, further comprising a decimal adder that outputs a numerical value that sums an output result of the 4-bit binary-decimal converter to a multiple of six. 4. The binary system according to claim 1, further comprising a decimal quadruple number generating circuit having a configuration in which a decimal double number generating circuit for doubling decimal data is connected in series in two stages. Decimal conversion circuit. 5. A double-decimal number is generated by the double-decimal number generating circuit, and the result is shifted to the left by 4 bits.
2. The binary-decimal conversion circuit according to claim 1, further comprising the decimal 20-multiple generation circuit that generates a 20-fold decimal number. 6. The data stored in the binary data register.
2. The system according to claim 1, further comprising the decimal data register for storing a decimal value after conversion of the decimal value.
Decimal-decimal conversion circuit. 7. The four most significant binary values to be converted
When the bits are output, a first step of shifting the binary value to the left by 4 bits to prepare for the next operation cycle, and converting the 4-bit binary value output in the first step to a 5-bit decimal value A second step of converting to a numerical value, a third step of generating 20 times and 4 times the decimal number generated in the previous operation cycle, and inversion of the 4 times number generated in the third step. Performing the fourth step, the decimal value obtained by the second step, and the 20th of the third step.
A fifth step in which a multiple is set as a first input, a quadruple inverted in the fourth step is set as a second input, and 1 is input to the carry to add and generate a decimal number; and a fifth step And a sixth step of holding the result generated in step (1) and outputting the result to the third step in the next operation cycle.