JPS592935B2 - multiplication circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplication circuit, and more particularly to a multiplication circuit designed to reduce table capacity when calculating products by table indexing.

When constructing a multiplier in which the multiplicand and the multiplier have a width of, for example, 8 bits, it is possible to divide the multiplicand and the multiplier into 4-bit widths as shown in Fig. 1, and configure them using a 4-bit wide multiplication table and an adder. A small multiplier can be constructed.

That is, in FIG. 1, 1 is a multiplication circuit, 100 and 101 are multiplicands (X7 to X), 102 and 103 are multipliers (X7 to Yo), 104 to 108 are inter-block connection lines, and 110 to 112 are multiplicands. and a multiplication table when the multiplier has a width of 4 bits, 114 and 115 represent adders, and 109 represents a product output line. In the figure, the multiplication table 110 is (X3 to X).

) and (Y7 to Y4) (al0 to a4
), 111 is (X7 to X4) and (Y3 to Y.
), 112 is (X3
Or X. ) and (Y. to Y.), 113 generates partial products (C15 not Lf, 8) of (X7 to X4) and (Y7 to Y4), and add them. The adder 114 adds the partial products (all to a4) (, b41 to b4), and the adder 115 adds the partial products (C15 to c.) and the output of the adder 114 to obtain the product (M15 to Mo). demand. Here, if the multiplication table tables 110 to 113 are configured with ROM,
Its capacity requires (decoder + 8 x 28 = 2048 bits), while it is divided into AND-OR matrix (J'L
When configured as A), its capacity is {(input-8×2)+(
Output 28)}×(number of terms 2225)=5400 bits are required. Furthermore, if the adder is constructed of PLA, a total capacity of 672 bits is required. To summarize the above, the 8-bit wide multiplier shown in Figure 1 can be realized entirely by PLA.
When stored in a chip, the total capacity is 5,400 x 4 + 672
= 22,272 bits, which is used as a bipolar IC.
It can be considered that it is impossible with the current manufacturing technology. In order to eliminate the above-mentioned drawbacks, the present invention reduces the capacity of a multiplication table whose multiplicands and multipliers are 4 bits wide, and constructs an 8-bit wide multiplier in one chip by combining the multiplicands and multipliers. The drawings will be described in detail below. The following two methods are conceivable for constructing a multiplicity table in which the bit width of the multiplicand and multiplier is 4 bits using PLA and reducing its capacity.

In other words, the first method takes advantage of the fact that the product XiXXj and the product XjXXi are the same in the multiplication table.
This is a method that uses 1) and 2) to make the multiplication table one.

However, since I only remember the product XiXXj, Xj
When obtaining the product XXi, an address conversion circuit is required to convert the product into the product XlXXj. The second method is to divide the table and provide an external decoder circuit for selecting the table. As the number of divisions increases, the table capacity becomes smaller, while the PLA capacity required for the decoder circuit increases, and there is a number of divisions that minimizes the total capacity. Generally, the optimum number of divisions is 2n, where n is the bit width of the multiplicand and the multiplier. For example, when n=4, 16 divisions is optimal. FIG. 2 shows an embodiment of the present invention, in which a multiplication circuit is constructed by incorporating each of the above two methods.

The code 100 in the figure is the multiplicand human power (X3 to X.), 1
03 is multiplier manual power (Y, to Y4), 104 is partial product output (All to A4), 200 is Xl, XO and Y5,
Comparison circuit for comparing the size with Y4, 213 is Xl,
Line 2 is O>Y,, Y4, 201 is X
203 to 212 based on the values of l, XO, Y5, Y4
202 is an address conversion circuit, and the line 213 is "
1", X3, X2, Y7, Y6 are sent as they are to line 215, while when line 213 is "1", Y7 is sent out.
, Y6, X3, X2 to line 215, 2
03 to 212 represent product matrices storing partial products. The matrix 203 is the product of (X3X2OO) and (Y7Y6OO), and the matrix 204 is the product of (X3X2OO)
The product of (X2OO) and (Y7Y6Ol) is expressed as matrix 2
05 is the product of (X3X2Ol) and (X7X6Ol),
The matrix 206 is (X3X2OO) and (Y7Y6lO
), the matrix 207 calculates the product of (X3X2Ol) and (
The matrix 208 is the product of (X3X
2lO) and (Y7Y6lO) in matrix 20
9 is the product of (X3X2OO) and (Y7Y6ll), and matrix 210 is (X3X2Ol) and (Y7Y6ll)
The matrix 211 is (X3X2lO) and (Y
7Y5ll), the matrix 212 is (X3X2
ll) and (Y7Y6ll), respectively. Further, the capacity of the product matrices 203, 205, 208, and 212 is reduced by applying the first method. Further, 216 to 225 are outputs of the selection circuit 201, (XlXOY
5Y4) is (0000), line 216 is (01
00) and (0001), the line 217 is changed to (01
01), the line 218 is changed to (1000) and (001
0), the line 219 is changed to (1001) and (011
0), line 220, (1010), line 221, (1100) and (0011), line 222, (1101) and (0111), line 223, (1110). When (1011), line 224 is selected, and when (1111), line 225 is selected.

For example, in Fig. 2, input 100 (X3X2XlXO
) as (0101) to input 103 (Y7Y6Y5Y
4), if (1110) is applied, the line 213 becomes "0" because X,
Since XOY5Y4), that is, (0110) is applied, the line 220 becomes "1", and the address conversion circuit 202
Then, since line 213 is "0" (X3, X2, Y
7, Y6) and sends (0111) to line 215. This integrated product matrix 207 is selected and outputs (01000110) to the output 104 as a partial product. Although the above description has been made regarding the multiplication table 110 shown in FIG. 1, the multiplication table tables 111 to 113 also have a similar configuration. If the configuration shown in Figure 2 is constructed using PLA, it can be configured with 2,614 bits or less, so the total capacity of the 8-bit wide multiplier shown in Figure 1 is 2,614 x 4 + 6.
It can be configured with 7211,128 bits or less, and can be configured with one chip using the current bipolar manufacturing technology.

Note that when the multiplier 1 shown in FIG.
This can be realized by connecting four digits, one 16-bit width digitizer, and one 24-bit width adder.

That is, by adding an adder to the multiplier 1 shown in FIG. 1, a highly expandable multiplier can be constructed. FIG. 3 shows an embodiment of an 8-bit wide multiplier according to the present invention, in which 1 is the same multiplier as shown in FIG. 1, 300 is a line for inputting partial products from other multipliers, 301 is a 16-bit wide adder, and 302 is a product output. For example, for a 16-bit multiplier, four multipliers shown in Figure 3 are installed, and three of the four multipliers are
This can be realized by appropriately connecting 00 and 302.
If the configuration shown in Figure 3 is realized with PLA, the capacity will be 1
It is possible to accommodate it on a chip. Although the embodiment of the multiplier with an 8-bit width has been described above, it goes without saying that the same can be applied even if the bit width changes.

As explained above, the present invention can configure a multiplier with a small total capacity when implemented as a PLA without significantly increasing the calculation time.

(1) An 8-bit wide multiplier can also be configured on one chip, (2) In order to provide further expandability, the above (
Even if a 16-bit width adder is added to the configuration of 1), it has the great advantage of being able to be configured on one chip.

[Brief explanation of the drawing]

FIG. 1 shows an example of a conventional 8-bit wide multiplier, FIG. 2 shows an example configuration of a 4-bit wide multiplication table used in the present invention, and FIG. 3 shows an 8-bit wide multiplier according to the present invention. An example is shown below. In the figure, 100 and 101 are multiplicand human power, 102 and 103 are multiplier human power, 104 to 108 are inter-block connection lines,
110 to 112 are multiplication tables, 114, 115
is an adder, 109 is a product output, 1 is an 8-bit wide multiplier, 2
00 is a comparison circuit, 213 is a comparison circuit output, 201 is a selection circuit, 216 to 225 are selection circuit outputs, 202 is an address conversion circuit, 203 to 212 are product matrices,
300 represents a partial product, 301 represents an adder, and 302 represents a product output.

Claims (1)

[Scope of Claims] 1. A multiplier that is provided with a partial product table that divides a partial product into a plurality of parts and stores them, and that indexes the partial product table using a given multiplier and multiplicand to obtain a product. a selection means for selecting the partial product table to be accessed based on the multiplicand and the multiplier; and a selection means for selecting the partial product table to be accessed based on the multiplicand and the multiplier; 1. A multiplication circuit comprising: address conversion means for converting in order; and a product obtained by indexing said plurality of partial product tables using information from said selection means and said address conversion means. 2. A patent claim characterized in that the multiplication circuit is configured to have an N-bit width output, a plurality of the multiplication circuits are arranged, and an addition circuit is provided for adding partial products from the plurality of multiplication circuits. The multiplier circuit according to the first term.