JPS5739460A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5739460A
JPS5739460A JP55113383A JP11338380A JPS5739460A JP S5739460 A JPS5739460 A JP S5739460A JP 55113383 A JP55113383 A JP 55113383A JP 11338380 A JP11338380 A JP 11338380A JP S5739460 A JPS5739460 A JP S5739460A
Authority
JP
Japan
Prior art keywords
circuit
inputted
ram5
buffer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55113383A
Other languages
Japanese (ja)
Inventor
Hidetaka Fujisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP55113383A priority Critical patent/JPS5739460A/en
Publication of JPS5739460A publication Critical patent/JPS5739460A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Calculators And Similar Devices (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)

Abstract

PURPOSE:To increase an operation speed in case of calculating a function, etc., by reading out contents of a specific register into a buffer, and indirectly designating an address to an RAM. CONSTITUTION:Each register of X, Y and Z is provided on an RAM5, and a data which is read out from the RAM5 is inputted to an operating circuit 17. This circuit 17 executes an operatio to an input data, stores its result in the RAM5, and also inputs it to a buffer 18. This buffer 18 reads the input data by prescribed timing, and its stored data is inputted to a B-counter 13 through a gate circuit 19. Subsequently, the uppermost bits of A and B counters 12, 13 are inputted to one-shot circuits 20, 21 , outputs of the circuit 20, 21 and a coincidence output of a coinciding circuit 10 are inputted to a latching circuit 23 through an OR circuit 22, and the circuit 23 delays the input signal by 1 digit portion, and outputs it to an ROM address part 3.
JP55113383A 1980-08-20 1980-08-20 Memory control system Pending JPS5739460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55113383A JPS5739460A (en) 1980-08-20 1980-08-20 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55113383A JPS5739460A (en) 1980-08-20 1980-08-20 Memory control system

Publications (1)

Publication Number Publication Date
JPS5739460A true JPS5739460A (en) 1982-03-04

Family

ID=14610903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55113383A Pending JPS5739460A (en) 1980-08-20 1980-08-20 Memory control system

Country Status (1)

Country Link
JP (1) JPS5739460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6113701A (en) * 1985-02-14 2000-09-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method, and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114839A (en) * 1975-04-02 1976-10-08 Hitachi Ltd Data processor
JPS53132955A (en) * 1977-04-25 1978-11-20 Hughes Aircraft Co Synchronous data processor
JPS5437645A (en) * 1977-08-31 1979-03-20 Toshiba Corp Computer system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114839A (en) * 1975-04-02 1976-10-08 Hitachi Ltd Data processor
JPS53132955A (en) * 1977-04-25 1978-11-20 Hughes Aircraft Co Synchronous data processor
JPS5437645A (en) * 1977-08-31 1979-03-20 Toshiba Corp Computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6113701A (en) * 1985-02-14 2000-09-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method, and system

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