JPS5736499A - Failure processing system for information processor - Google Patents

Failure processing system for information processor

Info

Publication number
JPS5736499A
JPS5736499A JP10906980A JP10906980A JPS5736499A JP S5736499 A JPS5736499 A JP S5736499A JP 10906980 A JP10906980 A JP 10906980A JP 10906980 A JP10906980 A JP 10906980A JP S5736499 A JPS5736499 A JP S5736499A
Authority
JP
Japan
Prior art keywords
failure
write
error correction
data
disable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10906980A
Other languages
Japanese (ja)
Inventor
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10906980A priority Critical patent/JPS5736499A/en
Publication of JPS5736499A publication Critical patent/JPS5736499A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To relieve intermittent error correction disable failure at partial byte write-in on a main memory, by using a cash memory. CONSTITUTION:When an error correction disable failure with a write-in request to a main memory 105 is reported 120 to a failed address control circuit 115, an error correction disable write-in failure report 122 is made to an execution unit 102. As a result, an error correction disable write-in failure processing firmware is started and readout request is made to a cash memory in a failed address 123. If the corresponding data is absent in the cash memory, the production of error correction disable and retrial disable failure is reported the same as the case with conventional methods, but if the data is present, the data is taken as write-in data and the failure address is taken as the write-in address, and the entire byte write-in request is outputted to correct the data of a main memory causing intermittent failure correctly.
JP10906980A 1980-08-08 1980-08-08 Failure processing system for information processor Pending JPS5736499A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10906980A JPS5736499A (en) 1980-08-08 1980-08-08 Failure processing system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10906980A JPS5736499A (en) 1980-08-08 1980-08-08 Failure processing system for information processor

Publications (1)

Publication Number Publication Date
JPS5736499A true JPS5736499A (en) 1982-02-27

Family

ID=14500802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10906980A Pending JPS5736499A (en) 1980-08-08 1980-08-08 Failure processing system for information processor

Country Status (1)

Country Link
JP (1) JPS5736499A (en)

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