JPS5622290A - Failure controlling system for memory unit - Google Patents

Failure controlling system for memory unit

Info

Publication number
JPS5622290A
JPS5622290A JP9577879A JP9577879A JPS5622290A JP S5622290 A JPS5622290 A JP S5622290A JP 9577879 A JP9577879 A JP 9577879A JP 9577879 A JP9577879 A JP 9577879A JP S5622290 A JPS5622290 A JP S5622290A
Authority
JP
Japan
Prior art keywords
error
address
circuit
readout
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9577879A
Other languages
Japanese (ja)
Inventor
Kazuyuki Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9577879A priority Critical patent/JPS5622290A/en
Publication of JPS5622290A publication Critical patent/JPS5622290A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the maintainability, by stacking the address information produced for error, restoring correct data in case of software error through retrial, and recognizing failed part in case of hardware error.
CONSTITUTION: When the ECC circuit 2 checks the data readout from the main memory unit 1 and detects the error, the error is corrected and set to the data register 3 and further, fed to the processing section 4, and simultaneously, the detection of error is informed to the control circuit 8 through the single error signal line 12. The circuit 8 stores the address in the address register 5 to the address stack memory 7. This operation is made every error detection and when the stack number of the memory 7 is n, the circuit 8 reads out one address from the memory 7 and sets it to the readout register 5 to start the readout from the unit 1. If error is taken place, it is written in the corrected data. When the error is detected through succeeding readout, the circuit 8 recognizes that fixed failure is produced in this address.
COPYRIGHT: (C)1981,JPO&Japio
JP9577879A 1979-07-27 1979-07-27 Failure controlling system for memory unit Pending JPS5622290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9577879A JPS5622290A (en) 1979-07-27 1979-07-27 Failure controlling system for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9577879A JPS5622290A (en) 1979-07-27 1979-07-27 Failure controlling system for memory unit

Publications (1)

Publication Number Publication Date
JPS5622290A true JPS5622290A (en) 1981-03-02

Family

ID=14146931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9577879A Pending JPS5622290A (en) 1979-07-27 1979-07-27 Failure controlling system for memory unit

Country Status (1)

Country Link
JP (1) JPS5622290A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57179996A (en) * 1981-04-27 1982-11-05 Nippon Telegr & Teleph Corp <Ntt> Semiconductor storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57179996A (en) * 1981-04-27 1982-11-05 Nippon Telegr & Teleph Corp <Ntt> Semiconductor storage device
JPS6135639B2 (en) * 1981-04-27 1986-08-14 Nippon Denshin Denwa Kk

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