JPS5731161A - Cmos integrated circuit - Google Patents

Cmos integrated circuit

Info

Publication number
JPS5731161A
JPS5731161A JP10620080A JP10620080A JPS5731161A JP S5731161 A JPS5731161 A JP S5731161A JP 10620080 A JP10620080 A JP 10620080A JP 10620080 A JP10620080 A JP 10620080A JP S5731161 A JPS5731161 A JP S5731161A
Authority
JP
Japan
Prior art keywords
wiring
region
cell
resin film
connecting hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10620080A
Other languages
Japanese (ja)
Inventor
Yasuhiko Nishikubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP10620080A priority Critical patent/JPS5731161A/en
Publication of JPS5731161A publication Critical patent/JPS5731161A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the degree of freedom of wiring and contrive the reduction of chip area, by providing a wiring region of bus line or the like on an MOST region by providing a connecting hole at the border between N-MOST and P- MOST. CONSTITUTION:In a CMOSIC, the first layer resin film 104 of polyimide is provided on the first layer metallic wiring 103 in a cell and then, a connecting hole 302 (110) is formed at the border between N-MOST (N channel MOSFET) and P- MOST, and the second metallic wiring 304 (105) is arranged on a cell 301. Furthermore, the second layer resin film 106 is stacked on the metallic wiring 304 (105) to provide a connecting hole 304 (111) and the third metallic wiring 305 (107) to protect them with the third resin film 108. By said constitution, a conventional wiring region arranged by keeping out of the cell is formed on the MOST region as predetermined shape, accordingly the degree of freedom of wiring between the input and output terminals and the P and N channel increases, and chip area can appreciably be reduced.
JP10620080A 1980-08-01 1980-08-01 Cmos integrated circuit Pending JPS5731161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10620080A JPS5731161A (en) 1980-08-01 1980-08-01 Cmos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10620080A JPS5731161A (en) 1980-08-01 1980-08-01 Cmos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5731161A true JPS5731161A (en) 1982-02-19

Family

ID=14427518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10620080A Pending JPS5731161A (en) 1980-08-01 1980-08-01 Cmos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5731161A (en)

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