JPS5723138A - Video display device - Google Patents

Video display device

Info

Publication number
JPS5723138A
JPS5723138A JP9834580A JP9834580A JPS5723138A JP S5723138 A JPS5723138 A JP S5723138A JP 9834580 A JP9834580 A JP 9834580A JP 9834580 A JP9834580 A JP 9834580A JP S5723138 A JPS5723138 A JP S5723138A
Authority
JP
Japan
Prior art keywords
data
circuit
signal
inverter
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9834580A
Other languages
Japanese (ja)
Other versions
JPH0157368B2 (en
Inventor
Hideji Yanase
Yoshitaka Omori
Osamu Suzuki
Hidefumi Matsuura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9834580A priority Critical patent/JPS5723138A/en
Publication of JPS5723138A publication Critical patent/JPS5723138A/en
Publication of JPH0157368B2 publication Critical patent/JPH0157368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory

Abstract

PURPOSE:To inhibit rewriting and to prevent a drawn pattern from being erased carelessly, by invalidating a write signal to an address where data which should not be erased is written. CONSTITUTION:Data read out of a digital memory 4 is inputted to a D/A converting circuit 5 for display on a CRT6 and also inputted to a coincidence circuit 9. Rewriting inhibition data A is also inputted to this coincidence circuit 9 previously, and the coincindence circuit 9 makes a comparison between both the input data and, when the two coincide with each other, sends a high-level coincidence signal to the other input terminal of an AND gate 11 via an inverter 10. Since this inverter 10 inverts and outputs the input signal, the inverter 10 generates a low level when both the input data to the coincidence circuit 9 coincide with each other or a high level when not, thereby sending a dissidence signal D.
JP9834580A 1980-07-17 1980-07-17 Video display device Granted JPS5723138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9834580A JPS5723138A (en) 1980-07-17 1980-07-17 Video display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9834580A JPS5723138A (en) 1980-07-17 1980-07-17 Video display device

Publications (2)

Publication Number Publication Date
JPS5723138A true JPS5723138A (en) 1982-02-06
JPH0157368B2 JPH0157368B2 (en) 1989-12-05

Family

ID=14217305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9834580A Granted JPS5723138A (en) 1980-07-17 1980-07-17 Video display device

Country Status (1)

Country Link
JP (1) JPS5723138A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5211824A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Display unit equipped with a write pen

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5211824A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Display unit equipped with a write pen

Also Published As

Publication number Publication date
JPH0157368B2 (en) 1989-12-05

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