JPS54112132A - Initial load system of control memory unit - Google Patents
Initial load system of control memory unitInfo
- Publication number
- JPS54112132A JPS54112132A JP2012578A JP2012578A JPS54112132A JP S54112132 A JPS54112132 A JP S54112132A JP 2012578 A JP2012578 A JP 2012578A JP 2012578 A JP2012578 A JP 2012578A JP S54112132 A JPS54112132 A JP S54112132A
- Authority
- JP
- Japan
- Prior art keywords
- information
- bit
- circuit
- registers
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To prevent the misuse of an error recovery circuit by adding a discrimination bit, which indicates whether write information is control information with no need of rewriting after initial loading or data to be rewritten likely, to the write information.
CONSTITUTION: Initial loader 3 reads out initial information, which includes an inversion bit and a data region indication bit, from external medium 2 to write data registers 301, 302 and 309. At this time, inversion bit 302 is "0" invariably, region indication bit 309 to be written in a control information region is "0", and one to be written in a data region is "1". Loader 3 writes contents of registers 301 and 302 into control memory unit 1, and comparator circuit 304 compares information read out from it with write information of registers. In this case, the output of AND circuit 305 between both the inversion bit and region indication bit is compared with information of "0" cia signal line 331 from unit 1. In this constitution, the output of circuit 304 is "1" in case of proper writing and "0" in case of improper writing, and rechecked after being inverted by inverter circuit 303, thereby discriminating whether proper writing is made or not.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53020125A JPS5830680B2 (en) | 1978-02-23 | 1978-02-23 | Control storage initial loading method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53020125A JPS5830680B2 (en) | 1978-02-23 | 1978-02-23 | Control storage initial loading method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54112132A true JPS54112132A (en) | 1979-09-01 |
JPS5830680B2 JPS5830680B2 (en) | 1983-06-30 |
Family
ID=12018391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53020125A Expired JPS5830680B2 (en) | 1978-02-23 | 1978-02-23 | Control storage initial loading method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5830680B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0628951A (en) * | 1992-04-08 | 1994-02-04 | Asahi Natl Shomei Kk | Rotary switch |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4881737U (en) * | 1971-12-30 | 1973-10-05 |
-
1978
- 1978-02-23 JP JP53020125A patent/JPS5830680B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4881737U (en) * | 1971-12-30 | 1973-10-05 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0628951A (en) * | 1992-04-08 | 1994-02-04 | Asahi Natl Shomei Kk | Rotary switch |
Also Published As
Publication number | Publication date |
---|---|
JPS5830680B2 (en) | 1983-06-30 |
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