JPS57179995A - Main memory error processing system - Google Patents

Main memory error processing system

Info

Publication number
JPS57179995A
JPS57179995A JP56062150A JP6215081A JPS57179995A JP S57179995 A JPS57179995 A JP S57179995A JP 56062150 A JP56062150 A JP 56062150A JP 6215081 A JP6215081 A JP 6215081A JP S57179995 A JPS57179995 A JP S57179995A
Authority
JP
Japan
Prior art keywords
main storage
error
data
gate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56062150A
Other languages
Japanese (ja)
Other versions
JPS6043544B2 (en
Inventor
Terutaka Tateishi
Minoru Etsuno
Kazuyuki Shimizu
Takamitsu Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56062150A priority Critical patent/JPS6043544B2/en
Publication of JPS57179995A publication Critical patent/JPS57179995A/en
Publication of JPS6043544B2 publication Critical patent/JPS6043544B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enable to report an error report to an access request circuit as an error of a main storage device, by providing a circuit which discriminates that a readout data is a specific data pattern.
CONSTITUTION: If an error is detected as the result of an inspection by a data error detecting circuit CO for main storage readout, a main storage readout data error signal SO turns on and an AND gate G2 is closed. A specific data pattern generating circuit C3 operates, a specific data pattern results in a buffer storage moving data D5 via an OR gate G8 and written in a buffer storage BS via a buffer storage write data register RO. In this case, the main storage readout data error signal S0 becomes a main storage error information producing signal S6 via an AND gate G5, and an OR gate G9 with a main storage readout data transmission instructing signal S4 and given to a main storage error information producing circuit C6.
COPYRIGHT: (C)1982,JPO&Japio
JP56062150A 1981-04-24 1981-04-24 Main memory error handling method Expired JPS6043544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56062150A JPS6043544B2 (en) 1981-04-24 1981-04-24 Main memory error handling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56062150A JPS6043544B2 (en) 1981-04-24 1981-04-24 Main memory error handling method

Publications (2)

Publication Number Publication Date
JPS57179995A true JPS57179995A (en) 1982-11-05
JPS6043544B2 JPS6043544B2 (en) 1985-09-28

Family

ID=13191780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56062150A Expired JPS6043544B2 (en) 1981-04-24 1981-04-24 Main memory error handling method

Country Status (1)

Country Link
JP (1) JPS6043544B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052250U (en) * 1983-09-17 1985-04-12 三笠産業株式会社 container spout

Also Published As

Publication number Publication date
JPS6043544B2 (en) 1985-09-28

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