JPS6043544B2 - Main memory error handling method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error method for data from main memory in a system having main memory and buffer storage.

Conventionally, when there is an error in the move-in data to the buffer memory, the process is to write the move-in data to the data section of the buffer memory but not to the address array section, or to write it to the address array section but there is an error. Therefore, there is a method to clear the address array section later.Also, when writing move-in data to the data section, it is also written to the address array section at the same time, but when writing to the data section, an error occurs because it is an error in the move-in data. There was a method of writing data in a specific data pattern that allowed errors to be determined when only a certain byte was read later.

In the first method, the move-in data cannot be written to the address array section until after it has been confirmed that there are no errors, resulting in a long processing time, and even bytes without errors are not stored in the buffer.

In the second method, the processing time is faster when there are no errors, but when there are errors, extra processing time is still required, and the drawbacks of the first method are that bytes with no errors cannot be stored in the buffer. It is.

The third method does not have the drawbacks of the first and second methods, but when a certain data pattern is later read out, it can be determined that it is an error, but it is recognized as an error in the incomplete memory. As a result, the retry function and configuration control function will perform useless processing assuming that there is a failure in the buffer storage. An object of the present invention is to provide a circuit that determines that data read from the buffer storage of the third method has a certain specific data pattern, and to report an error to an access request circuit when the data is a certain specific data pattern. The purpose is to make it possible to report errors not as buffer storage errors but as main storage errors. FIG. 1 schematically shows an embodiment of the present invention, in which 1 indicates a main memory, 2 a buffer memory, 3 an access control circuit, 4 an access request circuit, and 5 a main memory, and 6 a main memory. is a move-in data circuit, 7 is a read data sending circuit, 8 is an error information reporting circuit, 9 is a processing circuit, 10 is a data processing circuit,
Reference numeral 11 indicates a specific data pattern discrimination circuit.

FIG. 2 shows details of one embodiment of the present invention.
is a register, RO is a buffer storage write data register, R1 is a buffer storage read data register, R2 is a main memory read data register, R3 is a read data sending register, and R4 is an error information sending register.

Further, GO to G1 indicate negative gates, G2 to G7 indicate AND gates, and G8 to Gll indicate OR gates.
Further, CO to C6 are logic circuit networks, CO is a main memory read data error detection circuit, C1 is a buffer memory read data error detection circuit, C2 is a specific data pattern discrimination circuit, and C
3 is a specific data pattern generation circuit, C4 is a read control circuit, C5 is a buffer storage error status generation circuit, and C6 is a main storage error information generation circuit. Also DO~D5
is the data bus line, DO, Dl is the main memory read data, D
2 represents buffer storage read data, D3 and D4 represent sending data, and D5 represents buffer storage move-in data. Also, SO to S7 are information lines, SO is a main memory read data error signal, S1 is a buffer memory read data error signal, S2 is a specific data pattern recognition signal, S3 is a buffer memory read data sending command signal, and S4 is main memory read data. S5 is a buffer storage error information generation signal, S6 is a main memory error information generation signal, and S7 is an engineering signal. information on each. Aoi also exhibits buffer memory. In response to an access request from the access request circuit, if the storage information corresponding to the request does not exist in the buffer storage, the access control circuit transfers the storage information from the main storage device! Read information.

The main memory read data DO is passed through the main memory read data register R2, and is output to the AND gate G7 by the main memory read data sending command signal S4 from the read control circuit C4.
, the OR gate GlO, and the read data sending register R3 to the access request circuit.

At the same time, the main memory read data D1 is checked by the main memory read data error detection circuit CO, and if there is no error, the main memory read data signal SO is turned off, and the main memory read data D1 is checked by the AND gate G2 and the OR gate G.
The data becomes buffer storage move-in data D5 through buffer storage write data register RO, and is written into buffer storage Aoi through buffer storage write data register RO. Further, if an error is detected as a result of the inspection by the main memory read data error detection circuit CO, the main memory read data error signal SO. is turned on, the AND gate G2 is closed, the specific data pattern generation circuit C3 operates, and the specific data pattern passes through the OR gate G8 and becomes buffer memory move-in data D5, and is transferred to the buffer memory BS via the buffer memory write data register RO. written. At this time, the main memory read data error signal SO is the main memory read data sending signal S.
4, the main memory error information generation signal S6 is supplied to the main memory information generation circuit C6 via the AND gate G5 and the OR gate G9.The main memory error information generated here is sent to the OR gate Gll and the error information sending register R4. The error information S7 is sent to the real access request circuit via the error information S7. The above is the operation when there is no stored information in the buffer storage.

If stored information exists in the buffer storage, the stored information is read from the buffer storage.

The buffer memory read data D2 read out via the buffer memory read data register R1 is sent to an AND gate G6, an OR gate GlO, and further via a read data output register R3 in response to a buffer memory read data output command signal S3 from a read control circuit C4. At the same time as being sent to the access request circuit, the buffer storage read data D2 is checked by the buffer storage read data error detection circuit C1, and if there is an error, the buffer storage read data error signal S1 is turned on. At the same time, the buffer storage read data D2 is inspected by a specific data pattern discrimination circuit C2, and if it is a specific data pattern, the specific pattern recognition signal S2 is turned on. here,
When the buffer memory read data error signal S1 is on and the specific data pattern recognition signal S2 is off, the buffer memory read data error signal S1 is generated by the buffer memory read data sending command signal S3 via the AND gate G3 to generate breadth memory error information. The signal becomes a signal S5 and is supplied to the buffer storage error information generation circuit C5.

The buffer storage error information generated here is the OR gate G
The error information S7 is sent to the access request circuit via the error information sending register R4. Note that when the buffer memory read data error signal S1 is on and the specific data pattern recognition signal S2 is on, the AND gate G4,
Main memory error information generation signal S via AND gate G9
6 and is supplied to the main memory error information generation circuit C6. The main memory error information generated here becomes error information S7 via the OR gate Gll error information sending register R4 and is sent to the access request circuit. The above is the operation when the stored information exists in the buffer storage. As a result, the access request circuit takes in the sending data D4 and error information S7,
Error processing and data processing are performed correctly.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG. 2 is a detailed block diagram thereof. In the figure, 1 is a main memory, 2 is a buffer memory, 11 is a specific data discrimination circuit, and 8 is an error information reporting circuit.

Claims (1)

[Claims] 1 It has a main memory, a buffer memory corresponding to it, an access control circuit for them, and an access request circuit that issues an access request, and when storage information in response to an access request from the access request circuit does not exist in the buffer memory, the main memory If there is an error in the move-in data read from the main memory, in a system that registers a specific data pattern as move-in data in the buffer memory, when the data pattern is read from the buffer memory, there is an error in the main memory rather than an error in the buffer memory. An error processing method characterized by reporting an error to an access request circuit.