JPH0520880A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To match data in two semiconductor memory parts in the shortest time upon recovery from one side operation by performing power supply control for individual memory package upon occurrence of memory error in double write constitution. CONSTITUTION:Data are written two times successively from a host device through data lines (a), (b) into semiconductor memory parts 10, 40 in a semiconductor memory 5 having double write constitution. If memory error occurs in a memory package 101 at the time of second writing, power supply for only the package 101. is interrupted through a control signal line (d) at an error address containing section 80. Consequently, the memory 5 is operated only on the side of semiconductor memory part 40. When data are written two times from the host device into the memory part 40 and the memory part 10 is recovered to double writing state, count sections 20, 50 are compared in order to match the data of the memory parts 10, 40. Address data corresponding to the writing number of the difference are then transferred from the memory part 40 to the memory part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, when a memory error occurs in either the first or second semiconductor storage unit that has a double-write configuration, one lung operates in a normal semiconductor storage unit and maintenance of the semiconductor storage unit in which the memory error occurs And a method of matching data in the first semiconductor memory unit and the second semiconductor memory unit after performing the above.

[0002]

2. Description of the Related Art Conventionally, in this type of semiconductor memory device, when a memory error occurs in one of the first and second semiconductor memory parts when a double write configuration is performed, a normal semiconductor memory part has a single lung. After the operation and maintenance of the semiconductor memory unit in which the memory error has occurred, the data in the first semiconductor memory unit and the data in the second semiconductor memory unit are matched by copying all the data.

[0003]

In order to match the data of the above-mentioned conventional semiconductor memory device of the dual writing structure,
Since it was not possible to control the power supply of each package, all the data was copied, but this method has the disadvantage that it takes time to copy the data.

[0004]

According to another aspect of the present invention, there is provided a semiconductor memory device, which is the same as the first semiconductor memory part and the first semiconductor memory part during a write operation from a host device to the first semiconductor memory part. A second semiconductor memory unit for writing data,
A first counting unit that counts and stores the number of times data is written from the host device to the first semiconductor memory unit;
A second counting unit that counts and stores the number of times data is written from the host device to the second semiconductor storage unit;
A first data address section for storing a start address and an end address when writing data from the higher-level device to the first semiconductor storage section; and a data writing operation for writing data from the higher-level apparatus to the second semiconductor storage section A second data address section for storing a start address and an end address of the same, a copy interface for data transfer between the first semiconductor storage section and the second semiconductor storage section, and an individual memory package A power supply control unit for controlling the power supply of the memory, and an error address storage unit for sensing and storing an address where a memory error has occurred, and when data is written from the host device to the first semiconductor storage unit. A start address and an end address are stored in the first data address section, the number of times data is written is counted, and the first count section is stored. Memorizing means and a start address and an end address when data is written from the higher-level device to the second semiconductor memory unit are stored in the second data address unit, and the number of times data is written is counted to determine the first address. Two
Means for storing data in the counting unit and the power control by the information in the error address storage unit when a memory error occurs in either the first semiconductor storage unit or the second semiconductor storage unit in the double-write configuration. Memory error occurred in the memory unit Only the power supply of the package is cut off, and the memory of the same address is normal via the copy interface according to the information in the error address storage when the device recovers after the single lung operation in the double writing configuration. The means for copying the data from the package and the first counting unit and the second counting unit are compared, and if there is a difference in the count value, the semiconductor memory unit with a larger count value is used to count the data through the copy interface. Address of data changed from the first data address part and the second data address part by a difference Constructed and means for copying the data to know.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, a semiconductor memory device 5 includes a first semiconductor memory section 10 including a first counting section 20 and a first data address section 30, a second counting section 50 and a second counting section 50.
Second semiconductor memory unit 4 including a data address unit 60 of
0 and the power supply control unit 70 including the error address storage unit 80
It is composed of and. The first semiconductor memory unit 10 is connected to the host device via the data line a, to the power supply control unit 70 via the control signal line d, and to the second semiconductor memory unit 40 via the copy interface c. . The second semiconductor storage unit 40 is connected to the host device via the data line b and to the power supply control unit 70 via the control signal line e.

Next, the operation of this embodiment will be described.
It is assumed that data is written twice from the upper device to the semiconductor memory device 5 having the double-write configuration in the semiconductor memory portions 10 and 40 through the data lines a and b, respectively. If a memory error occurs in the memory package 101 by chance during the second write, the address of the memory package 101 is stored in the error address storage unit 80 using the control signal line d, and the power supply control unit 70 causes the memory package 1 to be stored.
Power off only 01. In this state, the semiconductor storage unit 5
Is the one-lung operation, which is the operation of only the second semiconductor storage unit 40. In this single lung operation state, when data is written twice from the upper device to the second semiconductor memory unit 40 via the data line b and then the first semiconductor memory unit 10 is restored and returns to the double writing state. The power supply control unit 70 copies data from the data of the error address storage unit 80 from the memory package 401 to the memory package 101 using the control signal line e via the copy interface c. After that, the first counting unit 20 and the second counting unit 50 are compared in order to match the data in the first semiconductor memory unit 10 and the data in the second semiconductor memory unit 40. Then, only the data addresses corresponding to the number of writes of the difference are known from the second data address section 60, and the data is transferred from the second semiconductor memory section 40 to the first semiconductor memory section 10 via the copy interface c.

[0009]

As described above, according to the present invention, by controlling the power supply of each memory package when a memory error occurs in the dual writing configuration, when the normal operation is restored after one lung operation, two semiconductor memories are stored. There is an effect that the data of the parts can be matched in the shortest time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

 5 semiconductor memory device 10 first semiconductor memory unit 20 first counting unit 30 first data address unit 40 second semiconductor memory unit 50 second counting unit 60 second data address unit 70 power control unit 80 error Address storage unit 101 to 107, 401 to 407 Memory package a Data line b Data line c Copy interface d Control signal line e Control signal line

Claims (1)

Claim: What is claimed is: 1. A first semiconductor memory unit and the first semiconductor memory unit during a write operation from a host device to the first semiconductor memory unit.
A second semiconductor memory unit for writing the same data as that of the semiconductor memory unit, a first counting unit for counting and storing the number of times of data writing from the higher-level device to the first semiconductor memory unit, and the higher-level device A second counting unit that counts and stores the number of times data is written to the second semiconductor memory unit, and stores a start address and an end address when writing data from the host device to the first semiconductor memory unit. A first data address section, a second data address section that stores a start address and an end address when writing data from the host device to the second semiconductor storage section, and the first semiconductor storage section A copy interface for data transfer with the second semiconductor memory unit, a power supply control unit for controlling the power supply of each memory package, and a memo. An error address storage unit for detecting and storing an address of an error occurrence, and a start address and an end address when data is written from the host device to the first semiconductor storage unit are stored in the first data address. Means for storing the data in the first counting unit and counting the number of times data is written,
A start address and an end address when data is written from the host device to the second semiconductor memory unit are stored in the second data address unit, the number of times data is written is counted, and the result is sent to the second counting unit. When a memory error occurs in either the first semiconductor storage unit or the second semiconductor storage unit in the dual writing configuration, a memory error occurs in the power supply control unit according to the information in the error address storage unit. A means for cutting off only the power supply of the generation package and the data from the memory package of the same normal address via the copy interface according to the information of the error address storage section when the one-lung operation in the dual writing configuration is recovered. The copy means and the first counting section and the second counting section are compared with each other, and if there is a difference in the count value, the count value is checked. And a means for copying the data by knowing the changed data address from the first data address part and the second data address part by the difference of the count from the semiconductor memory part having a large input value through the copy interface. A semiconductor memory device comprising: