JPS57212520A - Data transferring system - Google Patents

Data transferring system

Info

Publication number
JPS57212520A
JPS57212520A JP9876881A JP9876881A JPS57212520A JP S57212520 A JPS57212520 A JP S57212520A JP 9876881 A JP9876881 A JP 9876881A JP 9876881 A JP9876881 A JP 9876881A JP S57212520 A JPS57212520 A JP S57212520A
Authority
JP
Japan
Prior art keywords
data
processing
circuit
control
supplies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9876881A
Other languages
Japanese (ja)
Inventor
Masanori Saito
Toshio Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP9876881A priority Critical patent/JPS57212520A/en
Publication of JPS57212520A publication Critical patent/JPS57212520A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To eliminate a waiting time in the course of transfer of data, and to shorten the whole processing time, by transferring data of a storing circuit alternately at every one work to plural data processing circuits under the control of a controlling circuit. CONSTITUTION:Address generating parts 1a, 1b are alternately controlled by a control part 2, and at every one control, an address signal of 1 work portion is outputted. Subsequently, the control part 2 supplies a switching signal synchronizing with this control, to a switch 8, and the switch 8 switches the address signal alternately and supplies it to a storing circuit 3. In accordance with said supply, the storing circuit 3 transfers stored data to processing circuits 4, 5, and the processing circuits 4, 5 input this data. The processing circuits 4, 5 store a result of processing in a buffer memory 6, and whenever data of 1 word portion is collected, the buffer memory 6 transfers the stored data to a data processing circuit 7. The processing circuit 7 supplies the processed data to an external device.
JP9876881A 1981-06-25 1981-06-25 Data transferring system Pending JPS57212520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9876881A JPS57212520A (en) 1981-06-25 1981-06-25 Data transferring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9876881A JPS57212520A (en) 1981-06-25 1981-06-25 Data transferring system

Publications (1)

Publication Number Publication Date
JPS57212520A true JPS57212520A (en) 1982-12-27

Family

ID=14228562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9876881A Pending JPS57212520A (en) 1981-06-25 1981-06-25 Data transferring system

Country Status (1)

Country Link
JP (1) JPS57212520A (en)

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