JPS6446856A - Expanding system for extension memory - Google Patents

Expanding system for extension memory

Info

Publication number
JPS6446856A
JPS6446856A JP20310887A JP20310887A JPS6446856A JP S6446856 A JPS6446856 A JP S6446856A JP 20310887 A JP20310887 A JP 20310887A JP 20310887 A JP20310887 A JP 20310887A JP S6446856 A JPS6446856 A JP S6446856A
Authority
JP
Japan
Prior art keywords
memory
extension
capacity
circuit
task
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20310887A
Other languages
Japanese (ja)
Inventor
Masami Michino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20310887A priority Critical patent/JPS6446856A/en
Publication of JPS6446856A publication Critical patent/JPS6446856A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid such a case where the memory extension capacity of a system is mistakenly decided based on the memory extension capacity set at the designing time point of a basic device, by expanding the memory capacity within an extension memory device to cope with the multiple tasks. CONSTITUTION:An address register circuit 1 stores the data used when a logical address is converted into a physical address for each task. An extension memory circuit 2 uses the output of the circuit 1 as an input. A task register circuit 3 obtains a task number for actuation from a system bus to store it and supplies the storage output to the circuit 1. Then a control circuit 4 controls the circuits 1-3 respectively. The memory capacity is expanded within an extension memory device to cope with the multiple tasks. Thus it is possible to avoid such a case where the memory extension capacity of a system is mistakenly decided based on the memory extension capacity set at the designing time point of a basic device.
JP20310887A 1987-08-17 1987-08-17 Expanding system for extension memory Pending JPS6446856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20310887A JPS6446856A (en) 1987-08-17 1987-08-17 Expanding system for extension memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20310887A JPS6446856A (en) 1987-08-17 1987-08-17 Expanding system for extension memory

Publications (1)

Publication Number Publication Date
JPS6446856A true JPS6446856A (en) 1989-02-21

Family

ID=16468526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20310887A Pending JPS6446856A (en) 1987-08-17 1987-08-17 Expanding system for extension memory

Country Status (1)

Country Link
JP (1) JPS6446856A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238943A (en) * 1985-08-14 1987-02-19 Hitachi Ltd Multi-register setting system microcomputer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238943A (en) * 1985-08-14 1987-02-19 Hitachi Ltd Multi-register setting system microcomputer

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