JPS57204149A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57204149A
JPS57204149A JP8825781A JP8825781A JPS57204149A JP S57204149 A JPS57204149 A JP S57204149A JP 8825781 A JP8825781 A JP 8825781A JP 8825781 A JP8825781 A JP 8825781A JP S57204149 A JPS57204149 A JP S57204149A
Authority
JP
Japan
Prior art keywords
film
field region
cvd sio2
flattened
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8825781A
Other languages
Japanese (ja)
Other versions
JPH0334654B2 (en
Inventor
Akira Kurosawa
Sunao Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8825781A priority Critical patent/JPS57204149A/en
Priority to US06/384,648 priority patent/US4472874A/en
Priority to EP82105074A priority patent/EP0067419B1/en
Priority to DE8282105074T priority patent/DE3279916D1/en
Priority to CA000404883A priority patent/CA1191280A/en
Publication of JPS57204149A publication Critical patent/JPS57204149A/en
Publication of JPH0334654B2 publication Critical patent/JPH0334654B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Abstract

PURPOSE:To inhibit the generation of a parasitic channel in the side surface of a groove section by injecting an impurity to the side surface with excellent controllability. CONSTITUTION:A thermal oxide film 12 is formed to a P type silicon substrate 11, an element forming region is coated with a resist film 13, ions are implanted while using the film 13 as a mask and distributed as shown in 14, the silicon substrate 11 is etched while employing the same resist film 13 as a mask and a concave section is shaped, and a plasma CVD SiO2 film is deposited onto the whole surface. The plasma CVD SiO2 film 16 is left in a field region so that the grooves 15 are left to the boundary of the field region and the element forming region, the CVD SiO2 film 17 and a film 18 which can be flattened are shaped successively onto the whole surface, the surface is flattened, etching is conducted, and a silicon oxide film is buried into the field region approximately flatly.
JP8825781A 1981-06-10 1981-06-10 Manufacture of semiconductor device Granted JPS57204149A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP8825781A JPS57204149A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device
US06/384,648 US4472874A (en) 1981-06-10 1982-06-03 Method of forming planar isolation regions having field inversion regions
EP82105074A EP0067419B1 (en) 1981-06-10 1982-06-09 Method of manufacturing integrated circuit devices using dielectric isolation
DE8282105074T DE3279916D1 (en) 1981-06-10 1982-06-09 Method of manufacturing integrated circuit devices using dielectric isolation
CA000404883A CA1191280A (en) 1981-06-10 1982-06-10 Method of forming plunar isolation regions having field inversion regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8825781A JPS57204149A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57204149A true JPS57204149A (en) 1982-12-14
JPH0334654B2 JPH0334654B2 (en) 1991-05-23

Family

ID=13937815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8825781A Granted JPS57204149A (en) 1981-06-10 1981-06-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57204149A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423230A (en) * 1977-07-22 1979-02-21 Mitsubishi Rayon Eng Kk Controlling system of sulfur oxide discharge amount contained in the combustion gas

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423230A (en) * 1977-07-22 1979-02-21 Mitsubishi Rayon Eng Kk Controlling system of sulfur oxide discharge amount contained in the combustion gas

Also Published As

Publication number Publication date
JPH0334654B2 (en) 1991-05-23

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