JPS57203283A - Production of magnetic bubble memory chip - Google Patents

Production of magnetic bubble memory chip

Info

Publication number
JPS57203283A
JPS57203283A JP8652681A JP8652681A JPS57203283A JP S57203283 A JPS57203283 A JP S57203283A JP 8652681 A JP8652681 A JP 8652681A JP 8652681 A JP8652681 A JP 8652681A JP S57203283 A JPS57203283 A JP S57203283A
Authority
JP
Japan
Prior art keywords
layers
etching
plasma etching
memory chip
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8652681A
Other languages
Japanese (ja)
Other versions
JPS634276B2 (en
Inventor
Hideki Fujiwara
Niwaji Majima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8652681A priority Critical patent/JPS57203283A/en
Publication of JPS57203283A publication Critical patent/JPS57203283A/en
Publication of JPS634276B2 publication Critical patent/JPS634276B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: By efficiently remove insulating and Cr2O3 layers respectively at the production of a memory chip by using only a plane parallel plate type plasma etching device and applying plasma etching and spattering methods respectively under different atmospheres to open a window for a terminal electrode part.
CONSTITUTION: In order to form a terminal electrode part, a resist pattern 15 is formed on the surface of an wafer 12 obtained by applying protective layer 8 to the surface of Cr2O3 layers 4, 6 formed on the surfaces of a conductive pattern layer 3 and a driving pattern layer 7 formed on the surface of a nonmagnetic crystal layer 1 through insulating layers 2, 5. The insulating layers 8, 5 of the wafer 12 are etched at first by using "Freon " such as CF4 containing O2 in a plane parallel plate type plasma etching device 9 and then the remaining Cr2O3 layers 4, 6 are removed by the spattering effect under a different atmosphere such as gaseous Ag in the same device 9 to form a termrinal electrode 15. Thus, this method prevent a sample to be moved to another device for etching and improve thr efficiency of etching because of quick etching of respective layers.
COPYRIGHT: (C)1982,JPO&Japio
JP8652681A 1981-06-05 1981-06-05 Production of magnetic bubble memory chip Granted JPS57203283A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8652681A JPS57203283A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8652681A JPS57203283A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Publications (2)

Publication Number Publication Date
JPS57203283A true JPS57203283A (en) 1982-12-13
JPS634276B2 JPS634276B2 (en) 1988-01-28

Family

ID=13889429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8652681A Granted JPS57203283A (en) 1981-06-05 1981-06-05 Production of magnetic bubble memory chip

Country Status (1)

Country Link
JP (1) JPS57203283A (en)

Also Published As

Publication number Publication date
JPS634276B2 (en) 1988-01-28

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