JPS5720048A - Signal correcting circuit - Google Patents
Signal correcting circuitInfo
- Publication number
- JPS5720048A JPS5720048A JP9472080A JP9472080A JPS5720048A JP S5720048 A JPS5720048 A JP S5720048A JP 9472080 A JP9472080 A JP 9472080A JP 9472080 A JP9472080 A JP 9472080A JP S5720048 A JPS5720048 A JP S5720048A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- error
- channel
- signals
- redundancy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1809—Pulse code modulation systems for audio signals by interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Noise Elimination (AREA)
- Stereo-Broadcasting Methods (AREA)
- Stereophonic System (AREA)
Abstract
PURPOSE:To facilitate the correction of an error signal by suppressing the redundancy of a data signal by achieving reproduction by substituting a signal, having an occurring error, with a signal of the other channel by utilizing the strong mutual correlation between signals of channel. CONSTITUTION:Signals of two channels from input terminals 1a and 1b are applied to sample holding circuits 3a and 3b via LPFs 2a and 2b to be sampled and held with the control signal of a clock generating circuit 4. Those signals are extracted alternately in time-division mode by a multiplexer 6 under the control of the circuit 4 to be converted an A/D converter 6 into a PCM signal, which is recorded by a recorder 10 via an adder 8 for prescribed data array processing. The recorded signal is inputted to a digital arraying device 11 and a clock generating circuit 12 and if a demultiplexer 15 detects some error, a signal having the error is substituted by the signal of the other channel, which is reproduced to suppress the redundancy of a data signal, thus facilitating the correction of the error signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9472080A JPS5720048A (en) | 1980-07-11 | 1980-07-11 | Signal correcting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9472080A JPS5720048A (en) | 1980-07-11 | 1980-07-11 | Signal correcting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5720048A true JPS5720048A (en) | 1982-02-02 |
Family
ID=14117959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9472080A Pending JPS5720048A (en) | 1980-07-11 | 1980-07-11 | Signal correcting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5720048A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60146055A (en) * | 1983-12-29 | 1985-08-01 | ブラザー工業株式会社 | Knitting mesh controller of knitting machine |
-
1980
- 1980-07-11 JP JP9472080A patent/JPS5720048A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60146055A (en) * | 1983-12-29 | 1985-08-01 | ブラザー工業株式会社 | Knitting mesh controller of knitting machine |
JPH0341581B2 (en) * | 1983-12-29 | 1991-06-24 |
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