JPS57199337A - Frequency division circuit - Google Patents

Frequency division circuit

Info

Publication number
JPS57199337A
JPS57199337A JP8519481A JP8519481A JPS57199337A JP S57199337 A JPS57199337 A JP S57199337A JP 8519481 A JP8519481 A JP 8519481A JP 8519481 A JP8519481 A JP 8519481A JP S57199337 A JPS57199337 A JP S57199337A
Authority
JP
Japan
Prior art keywords
output
frequency division
gate
duty cycle
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8519481A
Other languages
Japanese (ja)
Inventor
Seiichi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8519481A priority Critical patent/JPS57199337A/en
Publication of JPS57199337A publication Critical patent/JPS57199337A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • H03K21/08Output circuits

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a desired odd number frequency division output of 50% duty cycle, by determining the number of stages of a ring counter and the number of inputs of gate deriving OR through a required frequency division number. CONSTITUTION:A gate 2 which derives output OR of (N/2) sets of a N notation ring counter 1, and an FF3 which utilizes the output of the gate 2 as a clear input and utilizes a clock corresponding to the logical NOT of an input clock of the counter 1 as a clock input, are provided, where indicates the Gauss symbol. An odd number frequency division output is obtained with 50% duty cycle. The gate 2 derives output logical sum of consecutive N/2 sets of outputs from QO+Q N/2 -1 out of the output of each stage. Then, the state of ''O'' for[N/2]t1 +(1/2)t1=(N/2)t1 and ''1'' for succeeding (N/2)t1 out of the Nt1 time is repeated ?at an OUT terminal in the period of Nt1. Thus, the frequency division output of 50% duty cycle can be obtained.
JP8519481A 1981-06-02 1981-06-02 Frequency division circuit Pending JPS57199337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8519481A JPS57199337A (en) 1981-06-02 1981-06-02 Frequency division circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8519481A JPS57199337A (en) 1981-06-02 1981-06-02 Frequency division circuit

Publications (1)

Publication Number Publication Date
JPS57199337A true JPS57199337A (en) 1982-12-07

Family

ID=13851833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8519481A Pending JPS57199337A (en) 1981-06-02 1981-06-02 Frequency division circuit

Country Status (1)

Country Link
JP (1) JPS57199337A (en)

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