JPS56129431A - Frequency dividing circuit for odd number - Google Patents

Frequency dividing circuit for odd number

Info

Publication number
JPS56129431A
JPS56129431A JP3267580A JP3267580A JPS56129431A JP S56129431 A JPS56129431 A JP S56129431A JP 3267580 A JP3267580 A JP 3267580A JP 3267580 A JP3267580 A JP 3267580A JP S56129431 A JPS56129431 A JP S56129431A
Authority
JP
Japan
Prior art keywords
output
circuit
frequency dividing
register
dividing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3267580A
Other languages
Japanese (ja)
Inventor
Yasuo Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3267580A priority Critical patent/JPS56129431A/en
Priority to CA000373034A priority patent/CA1150367A/en
Publication of JPS56129431A publication Critical patent/JPS56129431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
    • H03K23/505—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is an odd number

Landscapes

  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To form the odd number frequency dividing circuit in which the periodic pulse of 50% duty ratio is obtained, by inputting each output of N stage of shift registers and one of each inverting output, to the input of exclusive logical sum (EXOR) circuit inserted at the input section of N stages of shift registers. CONSTITUTION:In constituting 3-frequency-dividing circuit with 2 stages of shift registers 11, 12, the 4-frequency dividing circuit 13 is constituted by returning the inverting output C of the shift register 12 at the 2nd stage to the input of the shift register of the 1st stage, and the EX-OR circuit 14 is inserted to the clock pulse input section of the 4-frequency dividing circuit. When the clock pulse A inputs to the terminal 15 at the time t0, since the output D of the register 12 is 0 in the EX- OR circuit 14, the clock pulse A is remained as 1 and output of B is made, and the inverting output 1 is stored in the register 11 as the shift pulse. Next, the output B of the EX-OR circuit 14 rises at the same time as the output A at thme t2, 1 is stored in the register 12 and frequency dividing operation is sequentially made, allowing to obtain the period pulse with 3-frequency division and 50% duty ratio.
JP3267580A 1980-03-17 1980-03-17 Frequency dividing circuit for odd number Pending JPS56129431A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3267580A JPS56129431A (en) 1980-03-17 1980-03-17 Frequency dividing circuit for odd number
CA000373034A CA1150367A (en) 1980-03-17 1981-03-16 Circuit for odd frequency division of a given pulse train

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3267580A JPS56129431A (en) 1980-03-17 1980-03-17 Frequency dividing circuit for odd number

Publications (1)

Publication Number Publication Date
JPS56129431A true JPS56129431A (en) 1981-10-09

Family

ID=12365442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3267580A Pending JPS56129431A (en) 1980-03-17 1980-03-17 Frequency dividing circuit for odd number

Country Status (2)

Country Link
JP (1) JPS56129431A (en)
CA (1) CA1150367A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242617A (en) * 1985-08-19 1987-02-24 Nec Corp Odd frequency dividing counter
JPS6381424U (en) * 1986-11-12 1988-05-28
JPS63185323U (en) * 1987-05-20 1988-11-29
JPH034618A (en) * 1989-05-31 1991-01-10 Nec Eng Ltd Clock frequency division circuit
US5426682A (en) * 1990-11-28 1995-06-20 Fujitsu Limited Sequential logic circuit having state hold circuits
EP1487108A1 (en) * 2003-06-13 2004-12-15 Via Technologies, Inc. Frequency divider for RF transceiver

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242617A (en) * 1985-08-19 1987-02-24 Nec Corp Odd frequency dividing counter
JPS6381424U (en) * 1986-11-12 1988-05-28
JPS63185323U (en) * 1987-05-20 1988-11-29
JPH034618A (en) * 1989-05-31 1991-01-10 Nec Eng Ltd Clock frequency division circuit
US5426682A (en) * 1990-11-28 1995-06-20 Fujitsu Limited Sequential logic circuit having state hold circuits
EP1487108A1 (en) * 2003-06-13 2004-12-15 Via Technologies, Inc. Frequency divider for RF transceiver
US6995589B2 (en) 2003-06-13 2006-02-07 Via Technologies Inc. Frequency divider for RF transceiver

Also Published As

Publication number Publication date
CA1150367A (en) 1983-07-19

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